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[09/62] drm/i915/bdw: display stuff

Message ID 1383451680-11173-10-git-send-email-benjamin.widawsky@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ben Widawsky Nov. 3, 2013, 4:07 a.m. UTC
Just enough to make the code not barf...

Init BDW display to look like HSW. For the simulator this should be
fine, but this will probably require more work.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

Comments

Daniel Vetter Nov. 6, 2013, 8:13 a.m. UTC | #1
On Sat, Nov 02, 2013 at 09:07:07PM -0700, Ben Widawsky wrote:
> Just enough to make the code not barf...
> 
> Init BDW display to look like HSW. For the simulator this should be
> fine, but this will probably require more work.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  drivers/gpu/drm/i915/intel_sprite.c  | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0c2e83c..436b750 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10308,7 +10308,7 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.write_eld = ironlake_write_eld;
>  			dev_priv->display.modeset_global_resources =
>  				ivb_modeset_global_resources;
> -		} else if (IS_HASWELL(dev)) {
> +		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
>  			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
>  			dev_priv->display.write_eld = haswell_write_eld;
>  			dev_priv->display.modeset_global_resources =
> @@ -10339,6 +10339,7 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.queue_flip = intel_gen6_queue_flip;
>  		break;
>  	case 7:
> +	case 8:
>  		dev_priv->display.queue_flip = intel_gen7_queue_flip;

Since this patch's inception we've enabled RCS flips on gen7. I've added a
FIMXE(BDW) comment that this needs to be tested.
-Daniel

>  		break;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8afaad6..f8b265c 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1092,6 +1092,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>  		break;
>  
>  	case 7:
> +	case 8:
>  		if (IS_IVYBRIDGE(dev)) {
>  			intel_plane->can_scale = true;
>  			intel_plane->max_downscale = 2;
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0c2e83c..436b750 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10308,7 +10308,7 @@  static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.write_eld = ironlake_write_eld;
 			dev_priv->display.modeset_global_resources =
 				ivb_modeset_global_resources;
-		} else if (IS_HASWELL(dev)) {
+		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
 			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
 			dev_priv->display.write_eld = haswell_write_eld;
 			dev_priv->display.modeset_global_resources =
@@ -10339,6 +10339,7 @@  static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.queue_flip = intel_gen6_queue_flip;
 		break;
 	case 7:
+	case 8:
 		dev_priv->display.queue_flip = intel_gen7_queue_flip;
 		break;
 	}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8afaad6..f8b265c 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1092,6 +1092,7 @@  intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 		break;
 
 	case 7:
+	case 8:
 		if (IS_IVYBRIDGE(dev)) {
 			intel_plane->can_scale = true;
 			intel_plane->max_downscale = 2;