From patchwork Tue Nov 5 20:42:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 3143921 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 16BE89F407 for ; Tue, 5 Nov 2013 20:49:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CD891205CA for ; Tue, 5 Nov 2013 20:48:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C25F0205B3 for ; Tue, 5 Nov 2013 20:48:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C57761021BF; Tue, 5 Nov 2013 12:48:55 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CCC1102186 for ; Tue, 5 Nov 2013 12:42:54 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 05 Nov 2013 12:39:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,535,1378882800"; d="scan'208";a="404107464" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.98]) by orsmga001.jf.intel.com with SMTP; 05 Nov 2013 12:42:52 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 05 Nov 2013 22:42:46 +0200 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Nov 2013 22:42:31 +0200 Message-Id: <1383684151-595-5-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1383684151-595-1-git-send-email-ville.syrjala@linux.intel.com> References: <1383684151-595-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Add support for VLV GPLL bypass X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Supposedly all current SKUs use GPLL, but there could be ones in the future that do not. Add (at least theoretical) support for such things. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dd40925..d9b4c26 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -876,6 +876,7 @@ struct intel_gen6_power_mgmt { enum { LOW_POWER, BETWEEN, HIGH_POWER } power; bool enabled; + bool gpll_enabled; struct delayed_work delayed_resume_work; /* diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f5bb9b3..caec9fe 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4064,7 +4064,9 @@ static void valleyview_enable_rps(struct drm_device *dev) val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); - DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); + dev_priv->rps.gpll_enabled = val & 0x10; + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", + dev_priv->rps.gpll_enabled ? "yes" : "no"); DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); dev_priv->rps.cur_delay = (val >> 8) & 0xff; @@ -5943,6 +5945,17 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) { int div; + if (!dev_priv->rps.gpll_enabled) { + int hpll_freq = valleyview_get_vco(dev_priv); + + div = 0xee + (10 << 1) - val; + + if (WARN_ON(div == 0)) + return -1; + + return DIV_ROUND_CLOSEST(hpll_freq << 1, div); + } + /* 4 x czclk */ switch (dev_priv->mem_freq) { case 800: @@ -5965,6 +5978,15 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) { int mul; + if (!dev_priv->rps.gpll_enabled) { + int hpll_freq = valleyview_get_vco(dev_priv); + + if (WARN_ON(val == 0)) + return -1; + + return 0xee + (10 << 1) - DIV_ROUND_CLOSEST(hpll_freq << 1, val); + } + /* 4 x czclk */ switch (dev_priv->mem_freq) { case 800: