From patchwork Tue Nov 5 22:44:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 3144141 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B6ABEBEEB2 for ; Tue, 5 Nov 2013 22:45:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B5AD6205DA for ; Tue, 5 Nov 2013 22:45:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B7D4E2047D for ; Tue, 5 Nov 2013 22:45:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 925C3FB870 for ; Tue, 5 Nov 2013 14:45:48 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qc0-f179.google.com (mail-qc0-f179.google.com [209.85.216.179]) by gabe.freedesktop.org (Postfix) with ESMTP id 28838FB869 for ; Tue, 5 Nov 2013 14:44:34 -0800 (PST) Received: by mail-qc0-f179.google.com with SMTP id k18so5258989qcv.38 for ; Tue, 05 Nov 2013 14:44:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=thiOjp9quuEbTNY9fU/eKGcsDkoivB6U1TXGl3BvTZ8=; b=WolfLUBAd2XJwfmoZe70XT3uX4sD0UbsQA3b4x5BWq6Awb4ZlxyRzmHddxHMOCgjGO cZ/8mi103bPoj9SMZGpXE542IwHoibC2ejPxZsQ7fonpP5d5KR3TAZALtZB4Z3laFPK0 UyEwUR2cliUPvGQt/Nvg76BUIOCZIOhh3HFrFU6LMAMy5uHPtcD0hYJN2URA28SBDElE boXswTZH5wAO3cWZ3774zA9SAXmp+X/BVoCMWf1JHUfX5RRc1XXo5xBz3viMB3zm2oTv 5QiPPJuup/IqJbC/6MDwI282cspyGr2ZxXElYWQvXGrtTrTYeHiBHXK+dlsvqGzSwmTR GnKw== X-Received: by 10.229.47.71 with SMTP id m7mr13934497qcf.25.1383691474331; Tue, 05 Nov 2013 14:44:34 -0800 (PST) Received: from localhost.localdomain ([177.140.135.10]) by mx.google.com with ESMTPSA id 48sm39881760yhq.11.2013.11.05.14.44.33 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 05 Nov 2013 14:44:33 -0800 (PST) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Nov 2013 20:44:14 -0200 Message-Id: <1383691456-2564-2-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1383691456-2564-1-git-send-email-rodrigo.vivi@gmail.com> References: <1381848067-5269-1-git-send-email-rodrigo.vivi@gmail.com> <1383691456-2564-1-git-send-email-rodrigo.vivi@gmail.com> Subject: [Intel-gfx] [PATCH 2/4] drm/i915: Slice Shutdown: Allow setting number of slices on through sysfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch introduces a sysfs interface to easily allow dynamically switch slice config default behaviour between 1 or 2 slices. v2: use number of slices on (1,2) instead of half or full strings. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_sysfs.c | 53 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 64 +++++++++++++++++++++++++++++++++++++-- 4 files changed, 116 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 27073e8..5bd8d6f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1791,6 +1791,7 @@ struct drm_i915_file_private { #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) #define HAS_PSR(dev) (IS_HASWELL(dev)) +#define HAS_SLICE_SHUTDOWN(dev) (IS_HSW_GT3(dev) && i915_enable_rc6) #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index cef38fd..bf6dd95 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -117,6 +117,51 @@ static struct attribute_group rc6_attr_group = { .name = power_group_name, .attrs = rc6_attrs }; + +static ssize_t gt_slices_show(struct device *kdev, + struct device_attribute *attr, char *buf) +{ + struct drm_minor *minor = dev_to_drm_minor(kdev); + struct drm_device *dev = minor->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + return sprintf(buf, "%s\n", I915_READ(MI_PREDICATE_RESULT_2) == + LOWER_SLICE_ENABLED ? "2" : "1"); +} + +static ssize_t gt_slices_store(struct device *kdev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_minor *minor = dev_to_drm_minor(kdev); + struct drm_device *dev = minor->dev; + int ret; + int slices; + + ret = kstrtoint(buf, 10, &slices); + if (ret) + return ret; + + ret = intel_set_gt_slices(dev, slices); + if (ret) + return ret; + + return count; +} + +static DEVICE_ATTR(gt_slices, S_IRUGO | S_IWUSR, gt_slices_show, + gt_slices_store); + +static struct attribute *gt_slices_attrs[] = { + &dev_attr_gt_slices.attr, + NULL +}; + +static struct attribute_group gt_slices_attr_group = { + .name = power_group_name, + .attrs = gt_slices_attrs +}; + #endif static int l3_access_valid(struct drm_device *dev, loff_t offset) @@ -558,6 +603,12 @@ void i915_setup_sysfs(struct drm_device *dev) if (ret) DRM_ERROR("RC6 residency sysfs setup failed\n"); } + if (HAS_SLICE_SHUTDOWN(dev)) { + ret = sysfs_merge_group(&dev->primary->kdev->kobj, + >_slices_attr_group); + if (ret) + DRM_ERROR("GT slice config sysfs setup failed\n"); + } #endif if (HAS_L3_DPF(dev)) { ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs); @@ -597,5 +648,7 @@ void i915_teardown_sysfs(struct drm_device *dev) device_remove_bin_file(dev->primary->kdev, &dpf_attrs); #ifdef CONFIG_PM sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group); + sysfs_unmerge_group(&dev->primary->kdev->kobj, + >_slices_attr_group); #endif } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 42c3983..cf37741 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -836,6 +836,7 @@ void intel_set_power_well(struct drm_device *dev, bool enable); void intel_enable_gt_powersave(struct drm_device *dev); void intel_disable_gt_powersave(struct drm_device *dev); void ironlake_teardown_rc6(struct drm_device *dev); +int intel_set_gt_slices(struct drm_device *dev, int slices); void intel_init_gt_slices(struct drm_device *dev); void gen6_update_ring_freq(struct drm_device *dev); void gen6_rps_idle(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 02d1b1f..40ab76a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3869,14 +3869,72 @@ static void gen6_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv); } -void intel_init_gt_slices(struct drm_device *dev) +static int intel_set_gt_full(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (!IS_HSW_GT3(dev)) - return; + I915_WRITE(HSW_GT_SLICE_INFO, SLICE_SEL_BOTH); + /* Slices are enabled on RC6 exit */ + gen6_gt_force_wake_get(dev_priv); + + if (wait_for(((I915_READ(HSW_GT_SLICE_INFO) & SLICE_STATUS_MASK) == + SLICE_STATUS_BOTH_ON), 2000)) { + DRM_ERROR("Timeout enabling full gt slices\n"); + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + gen6_gt_force_wake_put(dev_priv); + return -ETIMEDOUT; + } I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + gen6_gt_force_wake_put(dev_priv); + + return 0; +} + +static int intel_set_gt_half(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + + /* Slices are disabled on RC6 exit */ + gen6_gt_force_wake_get(dev_priv); + + if (wait_for(((I915_READ(HSW_GT_SLICE_INFO) & SLICE_STATUS_MASK) == + SLICE_STATUS_MAIN_ON), 2000)) { + DRM_ERROR("Timed out disabling half gt slices\n"); + I915_WRITE(HSW_GT_SLICE_INFO, SLICE_SEL_BOTH); + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + gen6_gt_force_wake_put(dev_priv); + return -ETIMEDOUT; + } + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + gen6_gt_force_wake_put(dev_priv); + return 0; +} + +int intel_set_gt_slices(struct drm_device *dev, int slices) +{ + if (!HAS_SLICE_SHUTDOWN(dev)) + return -ENODEV; + + switch (slices) { + case 1: return intel_set_gt_half(dev); + case 2: return intel_set_gt_full(dev); + default: return -EINVAL; + } +} + +void intel_init_gt_slices(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (IS_HSW_GT3(dev)) + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + + if (!HAS_SLICE_SHUTDOWN(dev)) + return; if (i915_gt_slices == 1) { I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH);