diff mbox

[2/2] drm/i915: Fix GT wake FIFO free entries for VLV

Message ID 1384387200-21956-3-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Nov. 14, 2013, midnight UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On VLV the GTFIFOCTL register has other bits besides the number of free
entries in the GT wake FIFO. Apply a mask when we read th register to
make sure we don't misinterpret the number of free FIFO entries.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     | 3 ++-
 drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
 2 files changed, 5 insertions(+), 4 deletions(-)

Comments

Jesse Barnes Nov. 27, 2013, 5:04 p.m. UTC | #1 
On Thu, 14 Nov 2013 02:00:00 +0200
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On VLV the GTFIFOCTL register has other bits besides the number of free
> entries in the GT wake FIFO. Apply a mask when we read th register to
> make sure we don't misinterpret the number of free FIFO entries.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     | 3 ++-
>  drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
>  2 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e8f47de..e243105 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4860,7 +4860,8 @@
>  #define    GT_FIFO_IAWRERR			(1<<1)
>  #define    GT_FIFO_IARDERR			(1<<0)
>  
> -#define  GT_FIFO_FREE_ENTRIES			0x120008
> +#define  GTFIFOCTL				0x120008
> +#define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
>  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
>  
>  #define  HSW_IDICR				0x9008
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index a9849ab..71902c4 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -148,10 +148,10 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
>  
>  	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
>  		int loop = 500;
> -		u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
> +		u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
>  		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
>  			udelay(10);
> -			fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
> +			fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
>  		}
>  		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
>  			++ret;
> @@ -806,7 +806,7 @@ static int gen6_do_reset(struct drm_device *dev)
>  		dev_priv->uncore.funcs.force_wake_put(dev_priv);
>  
>  	/* Restore fifo count */
> -	dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
> +	dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
>  
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  	return ret;

I don't see this reg on HSW, but it looks like our HSW code uses this
routine?

Assuming the spec is just broken today... at least I see it for other
gens.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Daniel Vetter Nov. 27, 2013, 5:16 p.m. UTC | #2 
On Wed, Nov 27, 2013 at 09:04:38AM -0800, Jesse Barnes wrote:
> On Thu, 14 Nov 2013 02:00:00 +0200
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On VLV the GTFIFOCTL register has other bits besides the number of free
> > entries in the GT wake FIFO. Apply a mask when we read th register to
> > make sure we don't misinterpret the number of free FIFO entries.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h     | 3 ++-
> >  drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
> >  2 files changed, 5 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e8f47de..e243105 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4860,7 +4860,8 @@
> >  #define    GT_FIFO_IAWRERR			(1<<1)
> >  #define    GT_FIFO_IARDERR			(1<<0)
> >  
> > -#define  GT_FIFO_FREE_ENTRIES			0x120008
> > +#define  GTFIFOCTL				0x120008
> > +#define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
> >  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
> >  
> >  #define  HSW_IDICR				0x9008
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index a9849ab..71902c4 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -148,10 +148,10 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
> >  
> >  	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
> >  		int loop = 500;
> > -		u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
> > +		u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
> >  		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
> >  			udelay(10);
> > -			fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
> > +			fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
> >  		}
> >  		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
> >  			++ret;
> > @@ -806,7 +806,7 @@ static int gen6_do_reset(struct drm_device *dev)
> >  		dev_priv->uncore.funcs.force_wake_put(dev_priv);
> >  
> >  	/* Restore fifo count */
> > -	dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
> > +	dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
> >  
> >  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> >  	return ret;
> 
> I don't see this reg on HSW, but it looks like our HSW code uses this
> routine?
> 
> Assuming the spec is just broken today... at least I see it for other
> gens.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Both merged with a little note about this one here. We can back it out
again ;-)

Thanks, Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8f47de..e243105 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4860,7 +4860,8 @@ 
 #define    GT_FIFO_IAWRERR			(1<<1)
 #define    GT_FIFO_IARDERR			(1<<0)
 
-#define  GT_FIFO_FREE_ENTRIES			0x120008
+#define  GTFIFOCTL				0x120008
+#define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
 
 #define  HSW_IDICR				0x9008
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index a9849ab..71902c4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -148,10 +148,10 @@  static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 
 	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 		int loop = 500;
-		u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
+		u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 			udelay(10);
-			fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
+			fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 		}
 		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 			++ret;
@@ -806,7 +806,7 @@  static int gen6_do_reset(struct drm_device *dev)
 		dev_priv->uncore.funcs.force_wake_put(dev_priv);
 
 	/* Restore fifo count */
-	dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
+	dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 	return ret;