diff mbox

[1/2] drm/i915/vlv: correct promotion timer value for RC6 Timeout method.

Message ID 1385567043-14626-1-git-send-email-deepak.s@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

deepak.s@intel.com Nov. 27, 2013, 3:44 p.m. UTC 
From: Deepak S <deepak.s@intel.com>

For RC6 Timeout method, we need to set promotion timer to 1750 us ( 1367
* 1.28 us)

Signed-off-by: Deepak S <deepak.s@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Jesse Barnes Nov. 27, 2013, 5:19 p.m. UTC | #1 
On Wed, 27 Nov 2013 21:14:03 +0530
deepak.s@intel.com wrote:

> From: Deepak S <deepak.s@intel.com>
> 
> For RC6 Timeout method, we need to set promotion timer to 1750 us ( 1367
> * 1.28 us)
> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 04e9863..cf3d54d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4102,7 +4102,8 @@ static void valleyview_enable_rps(struct drm_device *dev)
>  	for_each_ring(ring, dev_priv, i)
>  		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>  
> -	I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
> +	/* Timer for RC6 Timeout Mode set to 1750 us ( 1367 * 1.28 us) */
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
>  
>  	/* allows RC6 residency counter to work */
>  	I915_WRITE(VLV_COUNTER_CONTROL,

Yeah I just sent this one too.  I'm fine with either one getting in.  I
also submitted one to do parallel restore of ring state, which we also
want.

Care to review my earlier ones?

http://lists.freedesktop.org/archives/intel-gfx/2013-November/036112.html
http://lists.freedesktop.org/archives/intel-gfx/2013-November/036111.html

Thanks,
deepak.s@intel.com Nov. 28, 2013, 3:35 a.m. UTC | #2 
Hi Jesse,

Your patches looks fine to me. I think lets go with your patches  and we can abandon mine.

Thanks
Deepak

-----Original Message-----
From: Jesse Barnes [mailto:jbarnes@virtuousgeek.org] 
Sent: Wednesday, November 27, 2013 10:50 PM
To: S, Deepak
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/vlv: correct promotion timer value for RC6 Timeout method.

On Wed, 27 Nov 2013 21:14:03 +0530
deepak.s@intel.com wrote:

> From: Deepak S <deepak.s@intel.com>
> 
> For RC6 Timeout method, we need to set promotion timer to 1750 us ( 
> 1367
> * 1.28 us)
> 
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> b/drivers/gpu/drm/i915/intel_pm.c index 04e9863..cf3d54d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4102,7 +4102,8 @@ static void valleyview_enable_rps(struct drm_device *dev)
>  	for_each_ring(ring, dev_priv, i)
>  		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>  
> -	I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
> +	/* Timer for RC6 Timeout Mode set to 1750 us ( 1367 * 1.28 us) */
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
>  
>  	/* allows RC6 residency counter to work */
>  	I915_WRITE(VLV_COUNTER_CONTROL,

Yeah I just sent this one too.  I'm fine with either one getting in.  I also submitted one to do parallel restore of ring state, which we also want.

Care to review my earlier ones?

http://lists.freedesktop.org/archives/intel-gfx/2013-November/036112.html
http://lists.freedesktop.org/archives/intel-gfx/2013-November/036111.html

Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
Daniel Vetter Nov. 28, 2013, 7:33 a.m. UTC | #3 
On Thu, Nov 28, 2013 at 03:35:45AM +0000, S, Deepak wrote:
> Hi Jesse,
> 
> Your patches looks fine to me. I think lets go with your patches  and we can abandon mine.

Does that count as a full Reviewed-by? If so please reply to the patches
with it.

Thanks, Daniel

> 
> Thanks
> Deepak
> 
> -----Original Message-----
> From: Jesse Barnes [mailto:jbarnes@virtuousgeek.org] 
> Sent: Wednesday, November 27, 2013 10:50 PM
> To: S, Deepak
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/vlv: correct promotion timer value for RC6 Timeout method.
> 
> On Wed, 27 Nov 2013 21:14:03 +0530
> deepak.s@intel.com wrote:
> 
> > From: Deepak S <deepak.s@intel.com>
> > 
> > For RC6 Timeout method, we need to set promotion timer to 1750 us ( 
> > 1367
> > * 1.28 us)
> > 
> > Signed-off-by: Deepak S <deepak.s@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c index 04e9863..cf3d54d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4102,7 +4102,8 @@ static void valleyview_enable_rps(struct drm_device *dev)
> >  	for_each_ring(ring, dev_priv, i)
> >  		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> >  
> > -	I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
> > +	/* Timer for RC6 Timeout Mode set to 1750 us ( 1367 * 1.28 us) */
> > +	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
> >  
> >  	/* allows RC6 residency counter to work */
> >  	I915_WRITE(VLV_COUNTER_CONTROL,
> 
> Yeah I just sent this one too.  I'm fine with either one getting in.  I also submitted one to do parallel restore of ring state, which we also want.
> 
> Care to review my earlier ones?
> 
> http://lists.freedesktop.org/archives/intel-gfx/2013-November/036112.html
> http://lists.freedesktop.org/archives/intel-gfx/2013-November/036111.html
> 
> Thanks,
> --
> Jesse Barnes, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
deepak.s@intel.com Nov. 28, 2013, 8:18 a.m. UTC | #4 
Yes I have reviewed both the patches.

Thanks
Deepak

-----Original Message-----
From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Thursday, November 28, 2013 1:03 PM
To: S, Deepak
Cc: Jesse Barnes; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/vlv: correct promotion timer value for RC6 Timeout method.

On Thu, Nov 28, 2013 at 03:35:45AM +0000, S, Deepak wrote:
> Hi Jesse,
> 
> Your patches looks fine to me. I think lets go with your patches  and we can abandon mine.

Does that count as a full Reviewed-by? If so please reply to the patches with it.

Thanks, Daniel

> 
> Thanks
> Deepak
> 
> -----Original Message-----
> From: Jesse Barnes [mailto:jbarnes@virtuousgeek.org]
> Sent: Wednesday, November 27, 2013 10:50 PM
> To: S, Deepak
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/vlv: correct promotion timer value for RC6 Timeout method.
> 
> On Wed, 27 Nov 2013 21:14:03 +0530
> deepak.s@intel.com wrote:
> 
> > From: Deepak S <deepak.s@intel.com>
> > 
> > For RC6 Timeout method, we need to set promotion timer to 1750 us (
> > 1367
> > * 1.28 us)
> > 
> > Signed-off-by: Deepak S <deepak.s@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c index 04e9863..cf3d54d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4102,7 +4102,8 @@ static void valleyview_enable_rps(struct drm_device *dev)
> >  	for_each_ring(ring, dev_priv, i)
> >  		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> >  
> > -	I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
> > +	/* Timer for RC6 Timeout Mode set to 1750 us ( 1367 * 1.28 us) */
> > +	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
> >  
> >  	/* allows RC6 residency counter to work */
> >  	I915_WRITE(VLV_COUNTER_CONTROL,
> 
> Yeah I just sent this one too.  I'm fine with either one getting in.  I also submitted one to do parallel restore of ring state, which we also want.
> 
> Care to review my earlier ones?
> 
> http://lists.freedesktop.org/archives/intel-gfx/2013-November/036112.h
> tml 
> http://lists.freedesktop.org/archives/intel-gfx/2013-November/036111.h
> tml
> 
> Thanks,
> --
> Jesse Barnes, Intel Open Source Technology Center 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 04e9863..cf3d54d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4102,7 +4102,8 @@  static void valleyview_enable_rps(struct drm_device *dev)
 	for_each_ring(ring, dev_priv, i)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 
-	I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+	/* Timer for RC6 Timeout Mode set to 1750 us ( 1367 * 1.28 us) */
+	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
 
 	/* allows RC6 residency counter to work */
 	I915_WRITE(VLV_COUNTER_CONTROL,