| Message ID | 1385720071-19587-1-git-send-email-deepak.s@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Nov 29, 2013 at 03:44:31PM +0530, deepak.s@intel.com wrote: > From: Deepak S <deepak.s@intel.com> > > On VLV, FIFO will be shared by both SW and HW. So, we read the > free entries through register and update dev_priv variable > and wait for only 20 entries to be free But the whole point of leaving 20 entries is for hardware has a portion of the fifo it can use for its own nefarious deeds. The hw has been emitting mmio through the write fifo since its inception on gen6, so what is so different for vlv? -Chris
Hi Chris, In VLV, both hardware and software can use the write fifo in parallel, we are adding this change as a water mark to make sure we atleast have 20 free entries .This will help us to avoid software mmio write being dropped. Thanks Deepak -----Original Message----- From: Chris Wilson [mailto:chris@chris-wilson.co.uk] Sent: Friday, November 29, 2013 4:09 PM To: S, Deepak Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 On Fri, Nov 29, 2013 at 03:44:31PM +0530, deepak.s@intel.com wrote: > From: Deepak S <deepak.s@intel.com> > > On VLV, FIFO will be shared by both SW and HW. So, we read the free > entries through register and update dev_priv variable and wait for > only 20 entries to be free But the whole point of leaving 20 entries is for hardware has a portion of the fifo it can use for its own nefarious deeds. The hw has been emitting mmio through the write fifo since its inception on gen6, so what is so different for vlv? -Chris -- Chris Wilson, Intel Open Source Technology Centre
On Fri, Nov 29, 2013 at 11:22:32AM +0000, S, Deepak wrote: > Hi Chris, > > In VLV, both hardware and software can use the write fifo in parallel, we are adding this change as a water mark to make sure we atleast have 20 free entries .This will help us to avoid software mmio write being dropped. Please think some more and describe the change exactly. -Chris
Sure Chris, I will recheck the spec and change the commit accordingly. -----Original Message----- From: Chris Wilson [mailto:chris@chris-wilson.co.uk] Sent: Friday, November 29, 2013 5:07 PM To: S, Deepak Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 On Fri, Nov 29, 2013 at 11:22:32AM +0000, S, Deepak wrote: > Hi Chris, > > In VLV, both hardware and software can use the write fifo in parallel, we are adding this change as a water mark to make sure we atleast have 20 free entries .This will help us to avoid software mmio write being dropped. Please think some more and describe the change exactly. -Chris
On Fri, Nov 29, 2013 at 11:53:44AM +0000, S, Deepak wrote: > Sure Chris, I will recheck the spec and change the commit accordingly. I guess the big question is why vlv is special. We've had these 20 fifo entries ever since gen6, so I'd also really like to know what suddenly changed. Even the 20 entries have just been copied from a spec with no explation. So if this is to allow hw writes to the gt from the display, then I guess we would need this change on all gen6+ platforms? Hence digging through specs or dragging a hw engineer into this discussion would be highly appreciated. Thanks, Daniel > > -----Original Message----- > From: Chris Wilson [mailto:chris@chris-wilson.co.uk] > Sent: Friday, November 29, 2013 5:07 PM > To: S, Deepak > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 > > On Fri, Nov 29, 2013 at 11:22:32AM +0000, S, Deepak wrote: > > Hi Chris, > > > > In VLV, both hardware and software can use the write fifo in parallel, we are adding this change as a water mark to make sure we atleast have 20 free entries .This will help us to avoid software mmio write being dropped. > > Please think some more and describe the change exactly. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[re-adding intel-gfx] On Tue, Dec 3, 2013 at 5:05 PM, S, Deepak <deepak.s@intel.com> wrote: > Hi Daniel/Chris, > > I spent some time in digging through the specs and also has chatted with couple of people. Below is my understanding of the FIFO. > > "On SB, Out of 64 FIFO Entries, 20 Entries will be used by HW and remaining 44 will be used by the SW,. I think due to this reason, we have a threshold of 20 Entries." > > "On VLV, HW and SW can access all 64 fifo entries, I don't think having a threshold of 20 Entries is mandatory on VLV. Also, since both SW and HW can access all 64 Entries. I think on VLV, we need to update the fifo_count before waiting for the FIFO." > > Please correct me if I am working. Looks sane. I've added this to the commit message and merged your patch. Thanks, Daniel > > Thanks > Deepak > > -----Original Message----- > From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter > Sent: Friday, November 29, 2013 7:33 PM > To: S, Deepak > Cc: Chris Wilson; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 > > On Fri, Nov 29, 2013 at 11:53:44AM +0000, S, Deepak wrote: >> Sure Chris, I will recheck the spec and change the commit accordingly. > > I guess the big question is why vlv is special. We've had these 20 fifo entries ever since gen6, so I'd also really like to know what suddenly changed. Even the 20 entries have just been copied from a spec with no explation. So if this is to allow hw writes to the gt from the display, then I guess we would need this change on all gen6+ platforms? > > Hence digging through specs or dragging a hw engineer into this discussion would be highly appreciated. > > Thanks, Daniel > >> >> -----Original Message----- >> From: Chris Wilson [mailto:chris@chris-wilson.co.uk] >> Sent: Friday, November 29, 2013 5:07 PM >> To: S, Deepak >> Cc: intel-gfx@lists.freedesktop.org >> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO >> and wait for 20 free entries. v2 >> >> On Fri, Nov 29, 2013 at 11:22:32AM +0000, S, Deepak wrote: >> > Hi Chris, >> > >> > In VLV, both hardware and software can use the write fifo in parallel, we are adding this change as a water mark to make sure we atleast have 20 free entries .This will help us to avoid software mmio write being dropped. >> >> Please think some more and describe the change exactly. >> -Chris >> >> -- >> Chris Wilson, Intel Open Source Technology Centre >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
Thanks Daniel. -----Original Message----- From: daniel.vetter@ffwll.ch [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter Sent: Wednesday, December 4, 2013 2:10 PM To: S, Deepak Cc: Chris Wilson; intel-gfx Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 [re-adding intel-gfx] On Tue, Dec 3, 2013 at 5:05 PM, S, Deepak <deepak.s@intel.com> wrote: > Hi Daniel/Chris, > > I spent some time in digging through the specs and also has chatted with couple of people. Below is my understanding of the FIFO. > > "On SB, Out of 64 FIFO Entries, 20 Entries will be used by HW and remaining 44 will be used by the SW,. I think due to this reason, we have a threshold of 20 Entries." > > "On VLV, HW and SW can access all 64 fifo entries, I don't think having a threshold of 20 Entries is mandatory on VLV. Also, since both SW and HW can access all 64 Entries. I think on VLV, we need to update the fifo_count before waiting for the FIFO." > > Please correct me if I am working. Looks sane. I've added this to the commit message and merged your patch. Thanks, Daniel > > Thanks > Deepak > > -----Original Message----- > From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of > Daniel Vetter > Sent: Friday, November 29, 2013 7:33 PM > To: S, Deepak > Cc: Chris Wilson; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO > and wait for 20 free entries. v2 > > On Fri, Nov 29, 2013 at 11:53:44AM +0000, S, Deepak wrote: >> Sure Chris, I will recheck the spec and change the commit accordingly. > > I guess the big question is why vlv is special. We've had these 20 fifo entries ever since gen6, so I'd also really like to know what suddenly changed. Even the 20 entries have just been copied from a spec with no explation. So if this is to allow hw writes to the gt from the display, then I guess we would need this change on all gen6+ platforms? > > Hence digging through specs or dragging a hw engineer into this discussion would be highly appreciated. > > Thanks, Daniel > >> >> -----Original Message----- >> From: Chris Wilson [mailto:chris@chris-wilson.co.uk] >> Sent: Friday, November 29, 2013 5:07 PM >> To: S, Deepak >> Cc: intel-gfx@lists.freedesktop.org >> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for >> FIFO and wait for 20 free entries. v2 >> >> On Fri, Nov 29, 2013 at 11:22:32AM +0000, S, Deepak wrote: >> > Hi Chris, >> > >> > In VLV, both hardware and software can use the write fifo in parallel, we are adding this change as a water mark to make sure we atleast have 20 free entries .This will help us to avoid software mmio write being dropped. >> >> Please think some more and describe the change exactly. >> -Chris >> >> -- >> Chris Wilson, Intel Open Source Technology Centre >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
[Dragging the discussion back to the public.] I agree that the 20 fifo limit is fairly arbitrary and it's still racy. Otoh that seems to be a bit that the hw engineers simply fumbled, so I guess we don't have much choice here. I've only merged the patch to dinq since there's no real report of this fixing anything and we have a bit of time to figure out something better. If there is such a thing even. Deepak, can you please poke hw engineers a bit how they've thought the driver should run this exactly? Thanks, Daniel On Wed, Dec 4, 2013 at 10:48 AM, S, Deepak <deepak.s@intel.com> wrote: > Agreed. But if we don't have a threshold, we might hit a high probability of dropping writes if HW or SW uses all 64 entries right?. > > Can we create a wq and check for the fifo entries at a periodic interval, this will reduce the fifo checking before every mmio write. > > Thank > Deepak S > > -----Original Message----- > From: Chris Wilson [mailto:chris@chris-wilson.co.uk] > Sent: Wednesday, December 4, 2013 3:04 PM > To: S, Deepak > Cc: Daniel Vetter > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 > > On Tue, Dec 03, 2013 at 04:05:07PM +0000, S, Deepak wrote: >> Hi Daniel/Chris, >> >> I spent some time in digging through the specs and also has chatted with couple of people. Below is my understanding of the FIFO. >> >> "On SB, Out of 64 FIFO Entries, 20 Entries will be used by HW and remaining 44 will be used by the SW,. I think due to this reason, we have a threshold of 20 Entries." >> >> "On VLV, HW and SW can access all 64 fifo entries, I don't think having a threshold of 20 Entries is mandatory on VLV. Also, since both SW and HW can access all 64 Entries. I think on VLV, we need to update the fifo_count before waiting for the FIFO." > > But there is also no point in waiting for at least 20 entries either. So the current code does not make sense for VLV in that light. Also note that the code is currently like it is as the mmio read before every write adds significant CPU overhead. There is also the problem that if the hw can consume the entire FIFO, it can also do so between us checking for a free entry and use performing the mmio. It seems to be broken by design... > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre
Hi Daniel, Sure, I don't have any contact with the hw engineer yet, I will try to get the right contact asap. Thanks Deepak -----Original Message----- From: daniel.vetter@ffwll.ch [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter Sent: Wednesday, December 4, 2013 4:37 PM To: S, Deepak Cc: Chris Wilson; intel-gfx Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 [Dragging the discussion back to the public.] I agree that the 20 fifo limit is fairly arbitrary and it's still racy. Otoh that seems to be a bit that the hw engineers simply fumbled, so I guess we don't have much choice here. I've only merged the patch to dinq since there's no real report of this fixing anything and we have a bit of time to figure out something better. If there is such a thing even. Deepak, can you please poke hw engineers a bit how they've thought the driver should run this exactly? Thanks, Daniel On Wed, Dec 4, 2013 at 10:48 AM, S, Deepak <deepak.s@intel.com> wrote: > Agreed. But if we don't have a threshold, we might hit a high probability of dropping writes if HW or SW uses all 64 entries right?. > > Can we create a wq and check for the fifo entries at a periodic interval, this will reduce the fifo checking before every mmio write. > > Thank > Deepak S > > -----Original Message----- > From: Chris Wilson [mailto:chris@chris-wilson.co.uk] > Sent: Wednesday, December 4, 2013 3:04 PM > To: S, Deepak > Cc: Daniel Vetter > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO > and wait for 20 free entries. v2 > > On Tue, Dec 03, 2013 at 04:05:07PM +0000, S, Deepak wrote: >> Hi Daniel/Chris, >> >> I spent some time in digging through the specs and also has chatted with couple of people. Below is my understanding of the FIFO. >> >> "On SB, Out of 64 FIFO Entries, 20 Entries will be used by HW and remaining 44 will be used by the SW,. I think due to this reason, we have a threshold of 20 Entries." >> >> "On VLV, HW and SW can access all 64 fifo entries, I don't think having a threshold of 20 Entries is mandatory on VLV. Also, since both SW and HW can access all 64 Entries. I think on VLV, we need to update the fifo_count before waiting for the FIFO." > > But there is also no point in waiting for at least 20 entries either. So the current code does not make sense for VLV in that light. Also note that the code is currently like it is as the mmio read before every write adds significant CPU overhead. There is also the problem that if the hw can consume the entire FIFO, it can also do so between us checking for a free entry and use performing the mmio. It seems to be broken by design... > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 0db5472..adf2b64 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -150,6 +150,13 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { int ret = 0; + /* On VLV, FIFO will be shared by both SW and HW. + * So, we need to read the FREE_ENTRIES everytime */ + if (IS_VALLEYVIEW(dev_priv->dev)) + dev_priv->uncore.fifo_count = + __raw_i915_read32(dev_priv, GTFIFOCTL & + GT_FIFO_FREE_ENTRIES_MASK); + if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;