From patchwork Sun Dec 8 08:22:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: deepak.s@intel.com X-Patchwork-Id: 3305791 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E18869F384 for ; Sun, 8 Dec 2013 08:22:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F2BD220348 for ; Sun, 8 Dec 2013 08:22:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3875C20340 for ; Sun, 8 Dec 2013 08:22:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1277AFA7FD; Sun, 8 Dec 2013 00:22:01 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CCAAFA7FC for ; Sun, 8 Dec 2013 00:21:59 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 08 Dec 2013 00:21:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,850,1378882800"; d="scan'208";a="446457720" Received: from deepaks.iind.intel.com ([10.223.82.165]) by fmsmga002.fm.intel.com with ESMTP; 08 Dec 2013 00:21:58 -0800 From: deepak.s@intel.com To: intel-gfx@lists.freedesktop.org Date: Sun, 8 Dec 2013 13:52:46 +0530 Message-Id: <1386490966-20678-1-git-send-email-deepak.s@intel.com> X-Mailer: git-send-email 1.8.4.2 Cc: Deepak S Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Bring UP Power Wells before disabling RC6. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Deepak S Instead of waiting for HW to bringup the wells, We force the wells up before disabling RC6. This is to avoid any register access when wells are down. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2e1340f..089712a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3661,6 +3661,12 @@ static void gen6_disable_rps(struct drm_device *dev) static void valleyview_disable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + unsigned long irqflags; + + /* We need to bring up the wells before disabling the RC6 */ + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); I915_WRITE(GEN6_RC_CONTROL, 0);