@@ -4982,6 +4982,7 @@
#define GEN6_GT_GFX_RC6 0x138108
#define GEN6_GT_GFX_RC6p 0x13810C
#define GEN6_GT_GFX_RC6pp 0x138110
+#define VLV_PCBR_ADDR_MASK 12
#define GEN6_PCODE_MAILBOX 0x138124
#define GEN6_PCODE_READY (1<<31)
@@ -4073,7 +4073,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
- u32 gtfifodbg, val, rc6_mode = 0;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -4118,7 +4118,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
VLV_MEDIA_RC6_COUNT_EN |
VLV_RENDER_RC6_COUNT_EN));
- if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
+
+ /* Enable RC6 Only if the PCBR address is configured either by
+ * BIOS or Gfx Driver */
+ pcbr = I915_READ(VLV_PCBR);
+ if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE &
+ (pcbr >> VLV_PCBR_ADDR_MASK))
rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
intel_print_rc6_info(dev, rc6_mode);