From patchwork Fri Dec 20 10:10:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 3387261 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BE4B29F37A for ; Fri, 20 Dec 2013 10:03:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 66380206F1 for ; Fri, 20 Dec 2013 10:03:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CAEFB206EF for ; Fri, 20 Dec 2013 10:03:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F393F9F1B; Fri, 20 Dec 2013 02:03:25 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id C6559F9F13 for ; Fri, 20 Dec 2013 02:03:01 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 20 Dec 2013 01:59:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,519,1384329600"; d="scan'208";a="427732395" Received: from vkannan-desktop.iind.intel.com ([10.223.25.35]) by orsmga001.jf.intel.com with ESMTP; 20 Dec 2013 02:02:59 -0800 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Dec 2013 15:40:55 +0530 Message-Id: <1387534258-5283-3-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387534258-5283-1-git-send-email-vandana.kannan@intel.com> References: <1387534258-5283-1-git-send-email-vandana.kannan@intel.com> Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Parse EDID probed modes for DRRS support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pradeep Bhat This patch and finds out the lowest refresh rate supported for the resolution same as the fixed_mode, based on the implementaion find_panel_downclock. It also checks the VBT fields to see if panel supports seamless DRRS or not. Based on above data it marks whether eDP panel supports seamless DRRS or not. This information is needed for supporting seamless DRRS switch for certain power saving usecases. This patch is tested by enabling the DRM logs and user should see whether Seamless DRRS is supported or not. v2: Daniel's review comments Modified downclock deduction based on intel_find_panel_downclock v3: Chris's review comments Moved edp_downclock_avail and edp_downclock to intel_panel v4: Jani's review comments. Changed name of the enum edp_panel_type to drrs_support type. Change is_drrs_supported to drrs_support of type enum drrs_support_type. Signed-off-by: Pradeep Bhat Signed-off-by: Vandana Kannan Reviewed-by: Daniel Vetter Reviewed-by: Chris Wilson Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dp.c | 45 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 30 +++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8f17f8f..079b53f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3522,6 +3522,46 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, I915_READ(pp_div_reg)); } +static void +intel_dp_drrs_initialize(struct intel_digital_port *intel_dig_port, + struct intel_connector *intel_connector, + struct drm_display_mode *fixed_mode) { + struct drm_connector *connector = &intel_connector->base; + struct intel_dp *intel_dp = &intel_dig_port->dp; + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + /** + * Check if PSR is supported by panel and enabled + * if so then DRRS is reported as not supported for Haswell. + */ + if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { + DRM_INFO("eDP panel has PSR enabled. Cannot support DRRS\n"); + return; + } + + /* First check if DRRS is enabled from VBT struct */ + if (!dev_priv->vbt.drrs_enabled) { + DRM_INFO("VBT doesn't support DRRS\n"); + return; + } + + intel_connector->panel.downclock_mode = intel_find_panel_downclock(dev, + fixed_mode, connector); + + if (intel_connector->panel.downclock_mode != NULL && + dev_priv->vbt.drrs_mode == SEAMLESS_DRRS_SUPPORT) { + intel_connector->panel.edp_downclock_avail = true; + intel_connector->panel.edp_downclock = + intel_connector->panel.downclock_mode->clock; + + intel_dp->drrs_state.drrs_support = dev_priv->vbt.drrs_mode; + + intel_dp->drrs_state.drrs_refresh_rate_type = DRRS_HIGH_RR; + DRM_INFO("SEAMLESS DRRS supported for eDP panel.\n"); + } +} + static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct intel_connector *intel_connector) { @@ -3535,6 +3575,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct drm_display_mode *scan; struct edid *edid; + intel_dp->drrs_state.drrs_support = DRRS_NOT_SUPPORTED; + if (!is_edp(intel_dp)) return true; @@ -3579,6 +3621,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, list_for_each_entry(scan, &connector->probed_modes, head) { if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { fixed_mode = drm_mode_duplicate(dev, scan); + if (INTEL_INFO(dev)->gen >= 5) + intel_dp_drrs_initialize(intel_dig_port, + intel_connector, fixed_mode); break; } } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index e903432..d208bf5 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -168,6 +168,9 @@ struct intel_panel { bool active_low_pwm; struct backlight_device *device; } backlight; + + bool edp_downclock_avail; + int edp_downclock; }; struct intel_connector { @@ -462,6 +465,32 @@ struct intel_hdmi { #define DP_MAX_DOWNSTREAM_PORTS 0x10 +/** + * This enum is used to indicate the DRRS support type. + */ +enum drrs_support_type { + DRRS_NOT_SUPPORTED = -1, + STATIC_DRRS_SUPPORT = 0, /* 1:1 mapping with VBT */ + SEAMLESS_DRRS_SUPPORT = 2 /* 1:1 mapping with VBT */ }; +/** + * HIGH_RR is the highest eDP panel refresh rate read from EDID + * LOW_RR is the lowest eDP panel refresh rate found from EDID + * parsing for same resolution. + */ +enum edp_drrs_refresh_rate_type { + DRRS_HIGH_RR, + DRRS_LOW_RR, + DRRS_MAX_RR, /* RR count */ +}; +/** + * The drrs_info struct will represent the DRRS feature for eDP + * panel. + */ +struct drrs_info { + enum drrs_support_type drrs_support; + enum edp_drrs_refresh_rate_type drrs_refresh_rate_type; +}; + struct intel_dp { uint32_t output_reg; uint32_t aux_ch_ctl_reg; @@ -487,6 +516,7 @@ struct intel_dp { bool want_panel_vdd; bool psr_setup_done; struct intel_connector *attached_connector; + struct drrs_info drrs_state; }; struct intel_digital_port {