From patchwork Thu Jan 9 11:26:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: akash.goel@intel.com X-Patchwork-Id: 3459161 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A64F2C02DC for ; Thu, 9 Jan 2014 11:25:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 800FD20122 for ; Thu, 9 Jan 2014 11:25:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6428020121 for ; Thu, 9 Jan 2014 11:25:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 40821106120; Thu, 9 Jan 2014 03:25:24 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id F2BD6106120 for ; Thu, 9 Jan 2014 03:25:21 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 09 Jan 2014 03:25:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,630,1384329600"; d="scan'208";a="462544813" Received: from akashgoe-desktop.iind.intel.com ([10.223.82.34]) by fmsmga002.fm.intel.com with ESMTP; 09 Jan 2014 03:25:04 -0800 From: akash.goel@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Jan 2014 16:56:38 +0530 Message-Id: <1389266799-13317-2-git-send-email-akash.goel@intel.com> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1389266799-13317-1-git-send-email-akash.goel@intel.com> References: <1389266799-13317-1-git-send-email-akash.goel@intel.com> Cc: Akash Goel Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Creating a new workqueue to handle MMIO flip work items X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel MMIO flips will replace the blitter command streamer based flips on VLV. Created our own private workqueue for handling the MMIO based flips, so as to avoid the block of the display thread (who issued the flip ioctl), due to the synchronization needed between the Rendering & flip stages. Now with MMIO based flips, the synchronization will require a wait in sw for the ongoing rendering operation, if any, to complete before issuing the flip. Because of this work queue, the wait on rendering to complete would be done by the worker thread. Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/i915_dma.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index ee9502b..ee4b445 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1609,6 +1609,29 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) goto out_mtrrfree; } + /* + * Creating our own private workqueue for handling the + * MMIO based flips. This is to avoid the block of the + * display thread (who issued the flip ioctl), due to the + * synchronization needed between the Rendering & flip stages. + * Now with MMIO based flips, the synchronization will require a + * wait in sw for the ongoing rendering operation, if any, to + * complete before issuing the flip. Because of this work queue, + * the wait on rendering would be done by the worker thread. + * + * Also since the flip work has to be processed at earliest, + * HIGHPRI flag is used here. We also use an ordered one, as + * we need serialized execution but anyways we support one + * outstanding flip call only, so probably doesn't really matter. + */ + dev_priv->flipwq = alloc_ordered_workqueue("i915_flip", WQ_HIGHPRI); + if (dev_priv->flipwq == NULL) { + DRM_ERROR("Failed to create flip workqueue.\n"); + ret = -ENOMEM; + destroy_workqueue(dev_priv->wq); + goto out_mtrrfree; + } + intel_irq_init(dev); intel_uncore_sanitize(dev); @@ -1685,6 +1708,7 @@ out_gem_unload: intel_teardown_gmbus(dev); intel_teardown_mchbar(dev); + destroy_workqueue(dev_priv->flipwq); destroy_workqueue(dev_priv->wq); out_mtrrfree: arch_phys_wc_del(dev_priv->gtt.mtrr); @@ -1792,6 +1816,7 @@ int i915_driver_unload(struct drm_device *dev) intel_teardown_mchbar(dev); destroy_workqueue(dev_priv->wq); + destroy_workqueue(dev_priv->flipwq); pm_qos_remove_request(&dev_priv->pm_qos); dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cc8afff..2e22430 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1451,6 +1451,7 @@ typedef struct drm_i915_private { * result in deadlocks. */ struct workqueue_struct *wq; + struct workqueue_struct *flipwq; /* Display functions */ struct drm_i915_display_funcs display;