From patchwork Thu Jan 9 15:08:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 3461451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EEBDF9F39F for ; Thu, 9 Jan 2014 15:08:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5F44C20134 for ; Thu, 9 Jan 2014 15:08:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A9A5120120 for ; Thu, 9 Jan 2014 15:08:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4C4FFB558; Thu, 9 Jan 2014 07:08:23 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 612BCFB537 for ; Thu, 9 Jan 2014 07:08:21 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 09 Jan 2014 07:08:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,631,1384329600"; d="scan'208";a="462631487" Received: from intelbox.fi.intel.com (HELO localhost) ([10.237.72.105]) by fmsmga002.fm.intel.com with ESMTP; 09 Jan 2014 07:08:19 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Jan 2014 17:08:16 +0200 Message-Id: <1389280096-1032-2-git-send-email-imre.deak@intel.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1389280096-1032-1-git-send-email-imre.deak@intel.com> References: <1389280096-1032-1-git-send-email-imre.deak@intel.com> Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915: vlv: W/a for hotplug/manual VGA detection X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP VGA detection requires the reference clock to be on, so make sure this is the case. This fixes VGA hotplug/manual detection where all pipes are off and so we would normally disable all clocks. v2: - Instead of disabling PSR clock gating, force the reference clock on through the DPLL_A register. (Kin Chan S ) v3: - Move enabling of the clock to intel_reset_dpio() and use the DPLL_B register instead, where we already have a similar tweak for the CRI clock. (Ville) Reported-by: Joonas Lahtinen Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3262ac4..4e2598b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1377,8 +1377,12 @@ static void intel_reset_dpio(struct drm_device *dev) if (!IS_VALLEYVIEW(dev)) return; - /* Enable the CRI clock source so we can get at the display */ + /* + * Enable the CRI clock source so we can get at the display and the + * reference clock for VGA hotplug / manual detection. + */ I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | + DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); /* @@ -1507,9 +1511,12 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) /* Make sure the pipe isn't still relying on us */ assert_pipe_disabled(dev_priv, pipe); - /* Leave integrated clock source enabled */ + /* + * Leave integrated clock source and reference clock enabled for pipe B. + * The latter is needed for VGA hotplug / manual detection. + */ if (pipe == PIPE_B) - val = DPLL_INTEGRATED_CRI_CLK_VLV; + val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; I915_WRITE(DPLL(pipe), val); POSTING_READ(DPLL(pipe)); } @@ -4986,7 +4993,11 @@ static void vlv_update_pll(struct intel_crtc *crtc) vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); - /* Enable DPIO clock input */ + /* + * Enable DPIO clock input. We should never disable the reference + * clock for pipe B, since VGA hotplug / manual detection depends + * on it. + */ dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; /* We should never disable this, set it here for state tracking */