diff mbox

[21/28] drm/i915: Drop WaDisableVDSUtnitClockGating:vlv

Message ID 1390419184-4450-22-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Jan. 22, 2014, 7:32 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableVDSUtnitClockGating was only relevant for early steepings of
VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ---
 1 file changed, 3 deletions(-)

Comments

Rodrigo Vivi Jan. 29, 2014, 1 p.m. UTC | #1 
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisableVDSUtnitClockGating was only relevant for early steepings of
> VLV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 593046a..1a45566 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4930,11 +4930,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>         /*
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
> -        *
> -        * Also apply WaDisableVDSUnitClockGating:vlv.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
> -                  GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
>                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 593046a..1a45566 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4930,11 +4930,8 @@  static void valleyview_init_clock_gating(struct drm_device *dev)
 	/*
 	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
-	 *
-	 * Also apply WaDisableVDSUnitClockGating:vlv.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
 		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);