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[22/28] drm/i915: Drop WaDisableTDLUnitClockGating:vlv

Message ID 1390419184-4450-23-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Jan. 22, 2014, 7:32 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 1 -
 1 file changed, 1 deletion(-)

Comments

Rodrigo Vivi Jan. 29, 2014, 1:01 p.m. UTC | #1 
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1a45566..dd68414 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4932,7 +4932,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
> -                  GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
>                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
>         /* WaDisableL3Bank2xClockGate:vlv */
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1a45566..dd68414 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4932,7 +4932,6 @@  static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableL3Bank2xClockGate:vlv */