| Message ID | 1390565594-9890-1-git-send-email-antti.koskipaa@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jan 24, 2014 at 02:13:14PM +0200, Antti Koskipaa wrote: > RFCv2: Reorganize array indexing so that full offsets can be used as > is. It makes grepping for registers in i915_reg.h much easier. Also > move offset arrays to intel_device_info. > > v1: Fixed offsets for VLV, proper eDP handling > > v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros. > > Upcoming hardware will not have the various display pipe register > ranges evenly spaced in memory. Change register address calculations > into array lookups. > > Tested on SNB, VLV, IVB and HSW w/eDP. > > I left the UMS cruft untouched. > > Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 44 ++++++++ > drivers/gpu/drm/i915/i915_drv.h | 11 +- > drivers/gpu/drm/i915/i915_reg.h | 229 ++++++++++++++++++++++------------------ > 3 files changed, 183 insertions(+), 101 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 62c0f16..3ac2ad2 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -157,16 +157,35 @@ MODULE_PARM_DESC(prefault_disable, > > static struct drm_driver driver; > > +#define GEN_DEFAULT_PIPEOFFSETS \ > + .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, PIPE_C_OFFSET }, \ > + .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ > + TRANSCODER_C_OFFSET, \ > + TRANSCODER_EDP_OFFSET }, \ > + .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \ > + .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ > + .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }, \ > + .trans_ddi_func_offsets = { TRANS_DDI_FUNC_CTL_A, \ > + TRANS_DDI_FUNC_CTL_B, \ > + TRANS_DDI_FUNC_CTL_C, \ > + TRANS_DDI_FUNC_CTL_EDP }, \ > + .trans_msa_misc_offsets = { TRANSA_MSA_MISC, TRANSB_MSA_MISC, \ > + TRANSC_MSA_MISC, TRANS_EDP_MSA_MISC }, > + > + > + > static const struct intel_device_info intel_i830_info = { > .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, > .has_overlay = 1, .overlay_needs_physical = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_845g_info = { > .gen = 2, .num_pipes = 1, > .has_overlay = 1, .overlay_needs_physical = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_i85x_info = { > @@ -175,18 +194,21 @@ static const struct intel_device_info intel_i85x_info = { > .has_overlay = 1, .overlay_needs_physical = 1, > .has_fbc = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_i865g_info = { > .gen = 2, .num_pipes = 1, > .has_overlay = 1, .overlay_needs_physical = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_i915g_info = { > .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, > .has_overlay = 1, .overlay_needs_physical = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > static const struct intel_device_info intel_i915gm_info = { > .gen = 3, .is_mobile = 1, .num_pipes = 2, > @@ -195,11 +217,13 @@ static const struct intel_device_info intel_i915gm_info = { > .supports_tv = 1, > .has_fbc = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > static const struct intel_device_info intel_i945g_info = { > .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, > .has_overlay = 1, .overlay_needs_physical = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > static const struct intel_device_info intel_i945gm_info = { > .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, > @@ -208,6 +232,7 @@ static const struct intel_device_info intel_i945gm_info = { > .supports_tv = 1, > .has_fbc = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_i965g_info = { > @@ -215,6 +240,7 @@ static const struct intel_device_info intel_i965g_info = { > .has_hotplug = 1, > .has_overlay = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_i965gm_info = { > @@ -223,6 +249,7 @@ static const struct intel_device_info intel_i965gm_info = { > .has_overlay = 1, > .supports_tv = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_g33_info = { > @@ -230,12 +257,14 @@ static const struct intel_device_info intel_g33_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .has_overlay = 1, > .ring_mask = RENDER_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_g45_info = { > .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, > .has_pipe_cxsr = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_gm45_info = { > @@ -244,18 +273,21 @@ static const struct intel_device_info intel_gm45_info = { > .has_pipe_cxsr = 1, .has_hotplug = 1, > .supports_tv = 1, > .ring_mask = RENDER_RING | BSD_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_pineview_info = { > .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, > .need_gfx_hws = 1, .has_hotplug = 1, > .has_overlay = 1, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_ironlake_d_info = { > .gen = 5, .num_pipes = 2, > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_ironlake_m_info = { > @@ -263,6 +295,7 @@ static const struct intel_device_info intel_ironlake_m_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .has_fbc = 1, > .ring_mask = RENDER_RING | BSD_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_sandybridge_d_info = { > @@ -271,6 +304,7 @@ static const struct intel_device_info intel_sandybridge_d_info = { > .has_fbc = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING, > .has_llc = 1, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_sandybridge_m_info = { > @@ -279,6 +313,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { > .has_fbc = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING, > .has_llc = 1, > + GEN_DEFAULT_PIPEOFFSETS > }; > > #define GEN7_FEATURES \ > @@ -291,18 +326,21 @@ static const struct intel_device_info intel_sandybridge_m_info = { > static const struct intel_device_info intel_ivybridge_d_info = { > GEN7_FEATURES, > .is_ivybridge = 1, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_ivybridge_m_info = { > GEN7_FEATURES, > .is_ivybridge = 1, > .is_mobile = 1, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_ivybridge_q_info = { > GEN7_FEATURES, > .is_ivybridge = 1, > .num_pipes = 0, /* legal, last one wins */ > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_valleyview_m_info = { > @@ -313,6 +351,7 @@ static const struct intel_device_info intel_valleyview_m_info = { > .display_mmio_offset = VLV_DISPLAY_BASE, > .has_fbc = 0, /* legal, last one wins */ > .has_llc = 0, /* legal, last one wins */ > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_valleyview_d_info = { > @@ -322,6 +361,7 @@ static const struct intel_device_info intel_valleyview_d_info = { > .display_mmio_offset = VLV_DISPLAY_BASE, > .has_fbc = 0, /* legal, last one wins */ > .has_llc = 0, /* legal, last one wins */ > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_haswell_d_info = { > @@ -330,6 +370,7 @@ static const struct intel_device_info intel_haswell_d_info = { > .has_ddi = 1, > .has_fpga_dbg = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_haswell_m_info = { > @@ -339,6 +380,7 @@ static const struct intel_device_info intel_haswell_m_info = { > .has_ddi = 1, > .has_fpga_dbg = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_broadwell_d_info = { > @@ -347,6 +389,7 @@ static const struct intel_device_info intel_broadwell_d_info = { > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .has_llc = 1, > .has_ddi = 1, > + GEN_DEFAULT_PIPEOFFSETS > }; > > static const struct intel_device_info intel_broadwell_m_info = { > @@ -355,6 +398,7 @@ static const struct intel_device_info intel_broadwell_m_info = { > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .has_llc = 1, > .has_ddi = 1, > + GEN_DEFAULT_PIPEOFFSETS > }; > > /* > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 29e1e86..1bb70a0 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -66,7 +66,8 @@ enum transcoder { > TRANSCODER_A = 0, > TRANSCODER_B, > TRANSCODER_C, > - TRANSCODER_EDP = 0xF, > + TRANSCODER_EDP, > + I915_MAX_TRANSCODERS > }; > #define transcoder_name(t) ((t) + 'A') > > @@ -506,6 +507,14 @@ struct intel_device_info { > u8 gen; > u8 ring_mask; /* Rings supported by the HW */ > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); > + /* Register offsets for the various display pipes and transcoders */ > + int pipe_offsets[I915_MAX_PIPES]; > + int trans_offsets[I915_MAX_TRANSCODERS]; > + int dpll_offsets[I915_MAX_PIPES]; > + int dpll_md_offsets[I915_MAX_PIPES]; > + int palette_offsets[I915_MAX_PIPES]; > + int trans_ddi_func_offsets[I915_MAX_TRANSCODERS]; > + int trans_msa_misc_offsets[I915_MAX_TRANSCODERS]; > }; > > #undef DEFINE_FLAG > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 76126e0..c5a5bd6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1202,6 +1202,10 @@ > /* > * Clock control & power management > */ > +#define DPLL_A_OFFSET 0x6014 > +#define DPLL_B_OFFSET 0x6018 > +#define DPLL(pipe) (dev_priv->info->dpll_offsets[pipe] + \ > + dev_priv->info->display_mmio_offset) > > #define VGA0 0x6000 > #define VGA1 0x6004 > @@ -1214,9 +1218,6 @@ > #define VGA1_PD_P1_DIV_2 (1 << 13) > #define VGA1_PD_P1_SHIFT 8 > #define VGA1_PD_P1_MASK (0x1f << 8) > -#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) > -#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) > -#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) > #define DPLL_VCO_ENABLE (1 << 31) > #define DPLL_SDVO_HIGH_SPEED (1 << 30) > #define DPLL_DVO_2X_MODE (1 << 30) > @@ -1278,7 +1279,12 @@ > #define SDVO_MULTIPLIER_MASK 0x000000ff > #define SDVO_MULTIPLIER_SHIFT_HIRES 4 > #define SDVO_MULTIPLIER_SHIFT_VGA 0 > -#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */ > + > +#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */ > +#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */ > +#define DPLL_MD(pipe) (dev_priv->info->dpll_md_offsets[pipe] + \ > + dev_priv->info->display_mmio_offset) > + > /* > * UDI pixel divider, controlling how many pixels are stuffed into a packet. > * > @@ -1315,8 +1321,6 @@ > */ > #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f > #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 > -#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */ > -#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) > > #define _FPA0 0x06040 > #define _FPA1 0x06044 > @@ -1472,10 +1476,10 @@ > /* > * Palette regs > */ > - > -#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) > -#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) > -#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) > +#define PALETTE_A_OFFSET 0xa000 > +#define PALETTE_B_OFFSET 0xa800 > +#define PALETTE(pipe) (dev_priv->info->palette_offsets[pipe] + \ > + dev_priv->info->display_mmio_offset) > > /* MCH MMIO space */ > > @@ -1939,35 +1943,45 @@ > _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000) > > /* Pipe A timing regs */ > -#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) > -#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) > -#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008) > -#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c) > -#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010) > -#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014) > -#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c) > -#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020) > -#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028) > +#define _HTOTAL_A 0x60000 > +#define _HBLANK_A 0x60004 > +#define _HSYNC_A 0x60008 > +#define _VTOTAL_A 0x6000c > +#define _VBLANK_A 0x60010 > +#define _VSYNC_A 0x60014 > +#define _PIPEASRC 0x6001c > +#define _BCLRPAT_A 0x60020 > +#define _VSYNCSHIFT_A 0x60028 > > /* Pipe B timing regs */ > -#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000) > -#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004) > -#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008) > -#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c) > -#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010) > -#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) > -#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) > -#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) > -#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) > - > -#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) > -#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) > -#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) > -#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) > -#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) > -#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) > -#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) > -#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) > +#define _HTOTAL_B 0x61000 > +#define _HBLANK_B 0x61004 > +#define _HSYNC_B 0x61008 > +#define _VTOTAL_B 0x6100c > +#define _VBLANK_B 0x61010 > +#define _VSYNC_B 0x61014 > +#define _PIPEBSRC 0x6101c > +#define _BCLRPAT_B 0x61020 > +#define _VSYNCSHIFT_B 0x61028 > + > +#define TRANSCODER_A_OFFSET 0x60000 > +#define TRANSCODER_B_OFFSET 0x61000 > +#define TRANSCODER_C_OFFSET 0x62000 > +#define TRANSCODER_EDP_OFFSET 0x6f000 > + > +#define _TRANSCODER2(pipe, reg) (dev_priv->info->trans_offsets[(pipe)] - \ > + dev_priv->info->trans_offsets[TRANSCODER_A] + (reg) + \ > + dev_priv->info->display_mmio_offset) > + > +#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) > +#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) > +#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) > +#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) > +#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) > +#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) > +#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) > +#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) > +#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) > > /* HSW+ eDP PSR registers */ > #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) > @@ -3173,10 +3187,10 @@ > /* Display & cursor control */ > > /* Pipe A */ > -#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000) > +#define _PIPEADSL 0x70000 > #define DSL_LINEMASK_GEN2 0x00000fff > #define DSL_LINEMASK_GEN3 0x00001fff > -#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) > +#define _PIPEACONF 0x70008 > #define PIPECONF_ENABLE (1<<31) > #define PIPECONF_DISABLE 0 > #define PIPECONF_DOUBLE_WIDE (1<<30) > @@ -3219,7 +3233,7 @@ > #define PIPECONF_DITHER_TYPE_ST1 (1<<2) > #define PIPECONF_DITHER_TYPE_ST2 (2<<2) > #define PIPECONF_DITHER_TYPE_TEMP (3<<2) > -#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024) > +#define _PIPEASTAT 0x70024 > #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) > #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) > #define PIPE_CRC_ERROR_ENABLE (1UL<<29) > @@ -3257,12 +3271,20 @@ > #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) > #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) > > -#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) > -#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) > -#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) > -#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) > -#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) > -#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) > +#define PIPE_A_OFFSET 0x70000 > +#define PIPE_B_OFFSET 0x71000 > +#define PIPE_C_OFFSET 0x72000 I'd like a comment here to explain what PIPE_EDP_OFFSET actually means. Eg.: /* * There's actually no pipe EDP. Some pipe registers have * simply shifted from the pipe to the transcoder, while * keeping their original offset. Thus we need PIPE_EDP_OFFSET * to access such registers in transcoder EDP. */ > +#define PIPE_EDP_OFFSET 0x7f000 > + > +#define _PIPE2(pipe, reg) (dev_priv->info->pipe_offsets[pipe] - \ > + dev_priv->info->pipe_offsets[PIPE_A] + (reg) + \ > + dev_priv->info->display_mmio_offset) > + > +#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) > +#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) > +#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) > +#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) > +#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) > > #define _PIPE_MISC_A 0x70030 > #define _PIPE_MISC_B 0x71030 > @@ -3274,7 +3296,7 @@ > #define PIPEMISC_DITHER_ENABLE (1<<4) > #define PIPEMISC_DITHER_TYPE_MASK (3<<2) > #define PIPEMISC_DITHER_TYPE_SP (0<<2) > -#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) > +#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) > > #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) > #define PIPEB_LINE_COMPARE_INT_EN (1<<29) > @@ -3515,7 +3537,7 @@ > #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) > > /* Display A control */ > -#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180) > +#define _DSPACNTR 0x70180 > #define DISPLAY_PLANE_ENABLE (1<<31) > #define DISPLAY_PLANE_DISABLE 0 > #define DISPPLANE_GAMMA_ENABLE (1<<30) > @@ -3549,25 +3571,25 @@ > #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) > #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ > #define DISPPLANE_TILED (1<<10) > -#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) > -#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188) > -#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */ > -#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190) > -#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */ > -#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */ > -#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */ > -#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC) > - > -#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) > -#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) > -#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) > -#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) > -#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) > -#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) > -#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) > +#define _DSPAADDR 0x70184 > +#define _DSPASTRIDE 0x70188 > +#define _DSPAPOS 0x7018C /* reserved */ > +#define _DSPASIZE 0x70190 > +#define _DSPASURF 0x7019C /* 965+ only */ > +#define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define _DSPAOFFSET 0x701A4 /* HSW */ > +#define _DSPASURFLIVE 0x701AC > + > +#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) > +#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) > +#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) > +#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) > +#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) > +#define DSPSURF(plane) _PIPE2(plane, _DSPASURF) > +#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) > #define DSPLINOFF(plane) DSPADDR(plane) > -#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) > -#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) > +#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) > +#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) > > /* Display/Sprite base address macros */ > #define DISP_BASEADDR_MASK (0xfffff000) > @@ -3863,48 +3885,45 @@ > #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff > > > -#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030) > +#define _PIPEA_DATA_M1 0x60030 > #define PIPE_DATA_M1_OFFSET 0 > -#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034) > +#define _PIPEA_DATA_N1 0x60034 > #define PIPE_DATA_N1_OFFSET 0 > > -#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038) > +#define _PIPEA_DATA_M2 0x60038 > #define PIPE_DATA_M2_OFFSET 0 > -#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c) > +#define _PIPEA_DATA_N2 0x6003c > #define PIPE_DATA_N2_OFFSET 0 > > -#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040) > +#define _PIPEA_LINK_M1 0x60040 > #define PIPE_LINK_M1_OFFSET 0 > -#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044) > +#define _PIPEA_LINK_N1 0x60044 > #define PIPE_LINK_N1_OFFSET 0 > > -#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048) > +#define _PIPEA_LINK_M2 0x60048 > #define PIPE_LINK_M2_OFFSET 0 > -#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c) > +#define _PIPEA_LINK_N2 0x6004c > #define PIPE_LINK_N2_OFFSET 0 > > /* PIPEB timing regs are same start from 0x61000 */ > > -#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030) > -#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034) > - > -#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038) > -#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c) > - > -#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040) > -#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044) > - > -#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048) > -#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c) > - > -#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) > -#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) > -#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) > -#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) > -#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) > -#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) > -#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) > -#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) > +#define _PIPEB_DATA_M1 0x61030 > +#define _PIPEB_DATA_N1 0x61034 > +#define _PIPEB_DATA_M2 0x61038 > +#define _PIPEB_DATA_N2 0x6103c > +#define _PIPEB_LINK_M1 0x61040 > +#define _PIPEB_LINK_N1 0x61044 > +#define _PIPEB_LINK_M2 0x61048 > +#define _PIPEB_LINK_N2 0x6104c > + > +#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) > +#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) > +#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) > +#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) > +#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) > +#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) > +#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) > +#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) > > /* CPU panel fitter */ > /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ > @@ -5175,8 +5194,8 @@ > #define TRANS_DDI_FUNC_CTL_B 0x61400 > #define TRANS_DDI_FUNC_CTL_C 0x62400 > #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 > -#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ > - TRANS_DDI_FUNC_CTL_B) > +#define TRANS_DDI_FUNC_CTL(tran) (dev_priv->info->trans_ddi_func_offsets[tran]) > + Why is there a separate offset for these? They're all within the normal transcoder range, aren't they? > #define TRANS_DDI_FUNC_ENABLE (1<<31) > /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ > #define TRANS_DDI_PORT_MASK (7<<28) > @@ -5343,10 +5362,12 @@ > #define TRANS_CLK_SEL_DISABLED (0x0<<29) > #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) > > -#define _TRANSA_MSA_MISC 0x60410 > -#define _TRANSB_MSA_MISC 0x61410 > -#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ > - _TRANSB_MSA_MISC) > +#define TRANSA_MSA_MISC 0x60410 > +#define TRANSB_MSA_MISC 0x61410 > +#define TRANSC_MSA_MISC 0x62410 > +#define TRANS_EDP_MSA_MISC 0x6f410 > +#define TRANS_MSA_MISC(tran) (dev_priv->info->trans_msa_misc_offsets[tran]) ditto > + > #define TRANS_MSA_SYNC_CLK (1<<0) > #define TRANS_MSA_6_BPC (0<<5) > #define TRANS_MSA_8_BPC (1<<5) > @@ -5854,4 +5875,12 @@ > #define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) > #define READ_DATA_VALID(n) (1 << (n)) > > +/* For UMS only (deprecated): */ > +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) > +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) > +#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) > +#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) > +#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) > +#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) > + > #endif /* _I915_REG_H_ */ > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 01/24/14 14:52, Ville Syrjälä wrote: > On Fri, Jan 24, 2014 at 02:13:14PM +0200, Antti Koskipaa wrote: >> +#define PIPE_A_OFFSET 0x70000 >> +#define PIPE_B_OFFSET 0x71000 >> +#define PIPE_C_OFFSET 0x72000 > > I'd like a comment here to explain what PIPE_EDP_OFFSET > actually means. Eg.: > > /* > * There's actually no pipe EDP. Some pipe registers have > * simply shifted from the pipe to the transcoder, while > * keeping their original offset. Thus we need PIPE_EDP_OFFSET > * to access such registers in transcoder EDP. > */ Ok. >> #define TRANS_DDI_FUNC_CTL_B 0x61400 >> #define TRANS_DDI_FUNC_CTL_C 0x62400 >> #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 >> -#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ >> - TRANS_DDI_FUNC_CTL_B) >> +#define TRANS_DDI_FUNC_CTL(tran) (dev_priv->info->trans_ddi_func_offsets[tran]) >> + > > Why is there a separate offset for these? They're all within the > normal transcoder range, aren't they? Yes, they are. Will use _TRANSCODER2 for those too. >> #define TRANS_DDI_FUNC_ENABLE (1<<31) >> /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ >> #define TRANS_DDI_PORT_MASK (7<<28) >> @@ -5343,10 +5362,12 @@ >> #define TRANS_CLK_SEL_DISABLED (0x0<<29) >> #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) >> >> -#define _TRANSA_MSA_MISC 0x60410 >> -#define _TRANSB_MSA_MISC 0x61410 >> -#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ >> - _TRANSB_MSA_MISC) >> +#define TRANSA_MSA_MISC 0x60410 >> +#define TRANSB_MSA_MISC 0x61410 >> +#define TRANSC_MSA_MISC 0x62410 >> +#define TRANS_EDP_MSA_MISC 0x6f410 >> +#define TRANS_MSA_MISC(tran) (dev_priv->info->trans_msa_misc_offsets[tran]) > > ditto Ditto.
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 62c0f16..3ac2ad2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -157,16 +157,35 @@ MODULE_PARM_DESC(prefault_disable, static struct drm_driver driver; +#define GEN_DEFAULT_PIPEOFFSETS \ + .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, PIPE_C_OFFSET }, \ + .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ + TRANSCODER_C_OFFSET, \ + TRANSCODER_EDP_OFFSET }, \ + .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \ + .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ + .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }, \ + .trans_ddi_func_offsets = { TRANS_DDI_FUNC_CTL_A, \ + TRANS_DDI_FUNC_CTL_B, \ + TRANS_DDI_FUNC_CTL_C, \ + TRANS_DDI_FUNC_CTL_EDP }, \ + .trans_msa_misc_offsets = { TRANSA_MSA_MISC, TRANSB_MSA_MISC, \ + TRANSC_MSA_MISC, TRANS_EDP_MSA_MISC }, + + + static const struct intel_device_info intel_i830_info = { .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, .has_overlay = 1, .overlay_needs_physical = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_845g_info = { .gen = 2, .num_pipes = 1, .has_overlay = 1, .overlay_needs_physical = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i85x_info = { @@ -175,18 +194,21 @@ static const struct intel_device_info intel_i85x_info = { .has_overlay = 1, .overlay_needs_physical = 1, .has_fbc = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i865g_info = { .gen = 2, .num_pipes = 1, .has_overlay = 1, .overlay_needs_physical = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i915g_info = { .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, .has_overlay = 1, .overlay_needs_physical = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i915gm_info = { .gen = 3, .is_mobile = 1, .num_pipes = 2, @@ -195,11 +217,13 @@ static const struct intel_device_info intel_i915gm_info = { .supports_tv = 1, .has_fbc = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i945g_info = { .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, .has_overlay = 1, .overlay_needs_physical = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i945gm_info = { .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, @@ -208,6 +232,7 @@ static const struct intel_device_info intel_i945gm_info = { .supports_tv = 1, .has_fbc = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i965g_info = { @@ -215,6 +240,7 @@ static const struct intel_device_info intel_i965g_info = { .has_hotplug = 1, .has_overlay = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_i965gm_info = { @@ -223,6 +249,7 @@ static const struct intel_device_info intel_i965gm_info = { .has_overlay = 1, .supports_tv = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_g33_info = { @@ -230,12 +257,14 @@ static const struct intel_device_info intel_g33_info = { .need_gfx_hws = 1, .has_hotplug = 1, .has_overlay = 1, .ring_mask = RENDER_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_g45_info = { .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, .has_pipe_cxsr = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_gm45_info = { @@ -244,18 +273,21 @@ static const struct intel_device_info intel_gm45_info = { .has_pipe_cxsr = 1, .has_hotplug = 1, .supports_tv = 1, .ring_mask = RENDER_RING | BSD_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_pineview_info = { .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, .need_gfx_hws = 1, .has_hotplug = 1, .has_overlay = 1, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_ironlake_d_info = { .gen = 5, .num_pipes = 2, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_ironlake_m_info = { @@ -263,6 +295,7 @@ static const struct intel_device_info intel_ironlake_m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .has_fbc = 1, .ring_mask = RENDER_RING | BSD_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_sandybridge_d_info = { @@ -271,6 +304,7 @@ static const struct intel_device_info intel_sandybridge_d_info = { .has_fbc = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING, .has_llc = 1, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_sandybridge_m_info = { @@ -279,6 +313,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { .has_fbc = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING, .has_llc = 1, + GEN_DEFAULT_PIPEOFFSETS }; #define GEN7_FEATURES \ @@ -291,18 +326,21 @@ static const struct intel_device_info intel_sandybridge_m_info = { static const struct intel_device_info intel_ivybridge_d_info = { GEN7_FEATURES, .is_ivybridge = 1, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_ivybridge_m_info = { GEN7_FEATURES, .is_ivybridge = 1, .is_mobile = 1, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_ivybridge_q_info = { GEN7_FEATURES, .is_ivybridge = 1, .num_pipes = 0, /* legal, last one wins */ + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_valleyview_m_info = { @@ -313,6 +351,7 @@ static const struct intel_device_info intel_valleyview_m_info = { .display_mmio_offset = VLV_DISPLAY_BASE, .has_fbc = 0, /* legal, last one wins */ .has_llc = 0, /* legal, last one wins */ + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_valleyview_d_info = { @@ -322,6 +361,7 @@ static const struct intel_device_info intel_valleyview_d_info = { .display_mmio_offset = VLV_DISPLAY_BASE, .has_fbc = 0, /* legal, last one wins */ .has_llc = 0, /* legal, last one wins */ + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_haswell_d_info = { @@ -330,6 +370,7 @@ static const struct intel_device_info intel_haswell_d_info = { .has_ddi = 1, .has_fpga_dbg = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_haswell_m_info = { @@ -339,6 +380,7 @@ static const struct intel_device_info intel_haswell_m_info = { .has_ddi = 1, .has_fpga_dbg = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_broadwell_d_info = { @@ -347,6 +389,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .has_llc = 1, .has_ddi = 1, + GEN_DEFAULT_PIPEOFFSETS }; static const struct intel_device_info intel_broadwell_m_info = { @@ -355,6 +398,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .has_llc = 1, .has_ddi = 1, + GEN_DEFAULT_PIPEOFFSETS }; /* diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 29e1e86..1bb70a0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -66,7 +66,8 @@ enum transcoder { TRANSCODER_A = 0, TRANSCODER_B, TRANSCODER_C, - TRANSCODER_EDP = 0xF, + TRANSCODER_EDP, + I915_MAX_TRANSCODERS }; #define transcoder_name(t) ((t) + 'A') @@ -506,6 +507,14 @@ struct intel_device_info { u8 gen; u8 ring_mask; /* Rings supported by the HW */ DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); + /* Register offsets for the various display pipes and transcoders */ + int pipe_offsets[I915_MAX_PIPES]; + int trans_offsets[I915_MAX_TRANSCODERS]; + int dpll_offsets[I915_MAX_PIPES]; + int dpll_md_offsets[I915_MAX_PIPES]; + int palette_offsets[I915_MAX_PIPES]; + int trans_ddi_func_offsets[I915_MAX_TRANSCODERS]; + int trans_msa_misc_offsets[I915_MAX_TRANSCODERS]; }; #undef DEFINE_FLAG diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 76126e0..c5a5bd6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1202,6 +1202,10 @@ /* * Clock control & power management */ +#define DPLL_A_OFFSET 0x6014 +#define DPLL_B_OFFSET 0x6018 +#define DPLL(pipe) (dev_priv->info->dpll_offsets[pipe] + \ + dev_priv->info->display_mmio_offset) #define VGA0 0x6000 #define VGA1 0x6004 @@ -1214,9 +1218,6 @@ #define VGA1_PD_P1_DIV_2 (1 << 13) #define VGA1_PD_P1_SHIFT 8 #define VGA1_PD_P1_MASK (0x1f << 8) -#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) -#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) -#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) #define DPLL_VCO_ENABLE (1 << 31) #define DPLL_SDVO_HIGH_SPEED (1 << 30) #define DPLL_DVO_2X_MODE (1 << 30) @@ -1278,7 +1279,12 @@ #define SDVO_MULTIPLIER_MASK 0x000000ff #define SDVO_MULTIPLIER_SHIFT_HIRES 4 #define SDVO_MULTIPLIER_SHIFT_VGA 0 -#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */ + +#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */ +#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */ +#define DPLL_MD(pipe) (dev_priv->info->dpll_md_offsets[pipe] + \ + dev_priv->info->display_mmio_offset) + /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * @@ -1315,8 +1321,6 @@ */ #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 -#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */ -#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) #define _FPA0 0x06040 #define _FPA1 0x06044 @@ -1472,10 +1476,10 @@ /* * Palette regs */ - -#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) -#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) -#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) +#define PALETTE_A_OFFSET 0xa000 +#define PALETTE_B_OFFSET 0xa800 +#define PALETTE(pipe) (dev_priv->info->palette_offsets[pipe] + \ + dev_priv->info->display_mmio_offset) /* MCH MMIO space */ @@ -1939,35 +1943,45 @@ _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000) /* Pipe A timing regs */ -#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) -#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) -#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008) -#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c) -#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010) -#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014) -#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c) -#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020) -#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028) +#define _HTOTAL_A 0x60000 +#define _HBLANK_A 0x60004 +#define _HSYNC_A 0x60008 +#define _VTOTAL_A 0x6000c +#define _VBLANK_A 0x60010 +#define _VSYNC_A 0x60014 +#define _PIPEASRC 0x6001c +#define _BCLRPAT_A 0x60020 +#define _VSYNCSHIFT_A 0x60028 /* Pipe B timing regs */ -#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000) -#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004) -#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008) -#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c) -#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010) -#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) -#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) -#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) -#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) - -#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) -#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) -#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) -#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) -#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) -#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) -#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) -#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) +#define _HTOTAL_B 0x61000 +#define _HBLANK_B 0x61004 +#define _HSYNC_B 0x61008 +#define _VTOTAL_B 0x6100c +#define _VBLANK_B 0x61010 +#define _VSYNC_B 0x61014 +#define _PIPEBSRC 0x6101c +#define _BCLRPAT_B 0x61020 +#define _VSYNCSHIFT_B 0x61028 + +#define TRANSCODER_A_OFFSET 0x60000 +#define TRANSCODER_B_OFFSET 0x61000 +#define TRANSCODER_C_OFFSET 0x62000 +#define TRANSCODER_EDP_OFFSET 0x6f000 + +#define _TRANSCODER2(pipe, reg) (dev_priv->info->trans_offsets[(pipe)] - \ + dev_priv->info->trans_offsets[TRANSCODER_A] + (reg) + \ + dev_priv->info->display_mmio_offset) + +#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) +#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) +#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) +#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) +#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) +#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) +#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) +#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) +#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) /* HSW+ eDP PSR registers */ #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) @@ -3173,10 +3187,10 @@ /* Display & cursor control */ /* Pipe A */ -#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000) +#define _PIPEADSL 0x70000 #define DSL_LINEMASK_GEN2 0x00000fff #define DSL_LINEMASK_GEN3 0x00001fff -#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) +#define _PIPEACONF 0x70008 #define PIPECONF_ENABLE (1<<31) #define PIPECONF_DISABLE 0 #define PIPECONF_DOUBLE_WIDE (1<<30) @@ -3219,7 +3233,7 @@ #define PIPECONF_DITHER_TYPE_ST1 (1<<2) #define PIPECONF_DITHER_TYPE_ST2 (2<<2) #define PIPECONF_DITHER_TYPE_TEMP (3<<2) -#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024) +#define _PIPEASTAT 0x70024 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) #define PIPE_CRC_ERROR_ENABLE (1UL<<29) @@ -3257,12 +3271,20 @@ #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) -#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) -#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) -#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) -#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) -#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) -#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) +#define PIPE_A_OFFSET 0x70000 +#define PIPE_B_OFFSET 0x71000 +#define PIPE_C_OFFSET 0x72000 +#define PIPE_EDP_OFFSET 0x7f000 + +#define _PIPE2(pipe, reg) (dev_priv->info->pipe_offsets[pipe] - \ + dev_priv->info->pipe_offsets[PIPE_A] + (reg) + \ + dev_priv->info->display_mmio_offset) + +#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) +#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) +#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) +#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) +#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) #define _PIPE_MISC_A 0x70030 #define _PIPE_MISC_B 0x71030 @@ -3274,7 +3296,7 @@ #define PIPEMISC_DITHER_ENABLE (1<<4) #define PIPEMISC_DITHER_TYPE_MASK (3<<2) #define PIPEMISC_DITHER_TYPE_SP (0<<2) -#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) +#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) #define PIPEB_LINE_COMPARE_INT_EN (1<<29) @@ -3515,7 +3537,7 @@ #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) /* Display A control */ -#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180) +#define _DSPACNTR 0x70180 #define DISPLAY_PLANE_ENABLE (1<<31) #define DISPLAY_PLANE_DISABLE 0 #define DISPPLANE_GAMMA_ENABLE (1<<30) @@ -3549,25 +3571,25 @@ #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ #define DISPPLANE_TILED (1<<10) -#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) -#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188) -#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */ -#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190) -#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */ -#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */ -#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */ -#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC) - -#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) -#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) -#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) -#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) -#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) -#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) -#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) +#define _DSPAADDR 0x70184 +#define _DSPASTRIDE 0x70188 +#define _DSPAPOS 0x7018C /* reserved */ +#define _DSPASIZE 0x70190 +#define _DSPASURF 0x7019C /* 965+ only */ +#define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define _DSPAOFFSET 0x701A4 /* HSW */ +#define _DSPASURFLIVE 0x701AC + +#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) +#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) +#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) +#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) +#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) +#define DSPSURF(plane) _PIPE2(plane, _DSPASURF) +#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) #define DSPLINOFF(plane) DSPADDR(plane) -#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) -#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) +#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) +#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK (0xfffff000) @@ -3863,48 +3885,45 @@ #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff -#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030) +#define _PIPEA_DATA_M1 0x60030 #define PIPE_DATA_M1_OFFSET 0 -#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034) +#define _PIPEA_DATA_N1 0x60034 #define PIPE_DATA_N1_OFFSET 0 -#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038) +#define _PIPEA_DATA_M2 0x60038 #define PIPE_DATA_M2_OFFSET 0 -#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c) +#define _PIPEA_DATA_N2 0x6003c #define PIPE_DATA_N2_OFFSET 0 -#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040) +#define _PIPEA_LINK_M1 0x60040 #define PIPE_LINK_M1_OFFSET 0 -#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044) +#define _PIPEA_LINK_N1 0x60044 #define PIPE_LINK_N1_OFFSET 0 -#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048) +#define _PIPEA_LINK_M2 0x60048 #define PIPE_LINK_M2_OFFSET 0 -#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c) +#define _PIPEA_LINK_N2 0x6004c #define PIPE_LINK_N2_OFFSET 0 /* PIPEB timing regs are same start from 0x61000 */ -#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030) -#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034) - -#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038) -#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c) - -#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040) -#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044) - -#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048) -#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c) - -#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) -#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) -#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) -#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) -#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) -#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) -#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) -#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) +#define _PIPEB_DATA_M1 0x61030 +#define _PIPEB_DATA_N1 0x61034 +#define _PIPEB_DATA_M2 0x61038 +#define _PIPEB_DATA_N2 0x6103c +#define _PIPEB_LINK_M1 0x61040 +#define _PIPEB_LINK_N1 0x61044 +#define _PIPEB_LINK_M2 0x61048 +#define _PIPEB_LINK_N2 0x6104c + +#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) +#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) +#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) +#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) +#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) +#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) +#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) +#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) /* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ @@ -5175,8 +5194,8 @@ #define TRANS_DDI_FUNC_CTL_B 0x61400 #define TRANS_DDI_FUNC_CTL_C 0x62400 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 -#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ - TRANS_DDI_FUNC_CTL_B) +#define TRANS_DDI_FUNC_CTL(tran) (dev_priv->info->trans_ddi_func_offsets[tran]) + #define TRANS_DDI_FUNC_ENABLE (1<<31) /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ #define TRANS_DDI_PORT_MASK (7<<28) @@ -5343,10 +5362,12 @@ #define TRANS_CLK_SEL_DISABLED (0x0<<29) #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) -#define _TRANSA_MSA_MISC 0x60410 -#define _TRANSB_MSA_MISC 0x61410 -#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ - _TRANSB_MSA_MISC) +#define TRANSA_MSA_MISC 0x60410 +#define TRANSB_MSA_MISC 0x61410 +#define TRANSC_MSA_MISC 0x62410 +#define TRANS_EDP_MSA_MISC 0x6f410 +#define TRANS_MSA_MISC(tran) (dev_priv->info->trans_msa_misc_offsets[tran]) + #define TRANS_MSA_SYNC_CLK (1<<0) #define TRANS_MSA_6_BPC (0<<5) #define TRANS_MSA_8_BPC (1<<5) @@ -5854,4 +5875,12 @@ #define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) #define READ_DATA_VALID(n) (1 << (n)) +/* For UMS only (deprecated): */ +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) +#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) +#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) +#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) +#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) + #endif /* _I915_REG_H_ */
RFCv2: Reorganize array indexing so that full offsets can be used as is. It makes grepping for registers in i915_reg.h much easier. Also move offset arrays to intel_device_info. v1: Fixed offsets for VLV, proper eDP handling v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros. Upcoming hardware will not have the various display pipe register ranges evenly spaced in memory. Change register address calculations into array lookups. Tested on SNB, VLV, IVB and HSW w/eDP. I left the UMS cruft untouched. Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 44 ++++++++ drivers/gpu/drm/i915/i915_drv.h | 11 +- drivers/gpu/drm/i915/i915_reg.h | 229 ++++++++++++++++++++++------------------ 3 files changed, 183 insertions(+), 101 deletions(-)