diff mbox

[5/9] drm/i915/bdw: Set rp_state_caps

Message ID 1390969547-1018-7-git-send-email-benjamin.widawsky@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ben Widawsky Jan. 29, 2014, 4:25 a.m. UTC 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

Comments

Rodrigo Vivi Feb. 6, 2014, 1:45 p.m. UTC | #1 
On Wed, Jan 29, 2014 at 2:25 AM, Ben Widawsky
<benjamin.widawsky@intel.com> wrote:
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6acb429..ae59bd9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3184,6 +3184,17 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
>         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
>  }
>
> +static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)

line over 80, but meh
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

> +{
> +       /* In units of 50MHz */
> +       dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
> +       dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
> +       dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
> +       dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
> +       dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
> +       dev_priv->rps.cur_delay = 0;
> +}
> +
>  static void gen8_enable_rps(struct drm_device *dev)
>  {
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3202,6 +3213,7 @@ static void gen8_enable_rps(struct drm_device *dev)
>         I915_WRITE(GEN6_RC_CONTROL, 0);
>
>         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> +       parse_rp_state_cap(dev_priv, rp_state_cap);
>
>         /* 2b: Program RC6 thresholds.*/
>         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> @@ -3288,13 +3300,7 @@ static void gen6_enable_rps(struct drm_device *dev)
>         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
>         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>
> -       /* In units of 50MHz */
> -       dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
> -       dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
> -       dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
> -       dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
> -       dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
> -       dev_priv->rps.cur_delay = 0;
> +       parse_rp_state_cap(dev_priv, rp_state_cap);
>
>         /* disable the counters and set deterministic thresholds */
>         I915_WRITE(GEN6_RC_CONTROL, 0);
> --
> 1.8.5.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
deepak.s@intel.com Feb. 7, 2014, 6:10 a.m. UTC | #2 
On Wed, Jan 29, 2014 at 9:55 AM, Ben Widawsky
> <benjamin.widawsky@intel.com <mailto:benjamin.widawsky@intel.com>> wrote:
>
>     Signed-off-by: Ben Widawsky <ben@bwidawsk.net <mailto:ben@bwidawsk.net>>
>     ---
>       drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++-------
>       1 file changed, 13 insertions(+), 7 deletions(-)
>
>     diff --git a/drivers/gpu/drm/i915/intel_pm.c
>     b/drivers/gpu/drm/i915/intel_pm.c
>     index 6acb429..ae59bd9 100644
>     --- a/drivers/gpu/drm/i915/intel_pm.c
>     +++ b/drivers/gpu/drm/i915/intel_pm.c
>     @@ -3184,6 +3184,17 @@ static void gen6_enable_rps_interrupts(struct
>     drm_device *dev)
>              I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
>       }
>
>     +static void parse_rp_state_cap(struct drm_i915_private *dev_priv,
>     u32 rp_state_cap)
>     +{
>     +       /* In units of 50MHz */
>     +       dev_priv->rps.hw_max = dev_priv->rps.max_delay =
>     rp_state_cap & 0xff;
>     +       dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
>     +       dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
>     +       dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
>     +       dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
>     +       dev_priv->rps.cur_delay = 0;
>     +}
>     +
>       static void gen8_enable_rps(struct drm_device *dev)
>       {
>              struct drm_i915_private *dev_priv = dev->dev_private;
>     @@ -3202,6 +3213,7 @@ static void gen8_enable_rps(struct drm_device
>     *dev)
>              I915_WRITE(GEN6_RC_CONTROL, 0);
>
>              rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
>     +       parse_rp_state_cap(dev_priv, rp_state_cap);
>
>              /* 2b: Program RC6 thresholds.*/
>              I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>     @@ -3288,13 +3300,7 @@ static void gen6_enable_rps(struct drm_device
>     *dev)
>              rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
>              gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>
>     -       /* In units of 50MHz */
>     -       dev_priv->rps.hw_max = dev_priv->rps.max_delay =
>     rp_state_cap & 0xff;
>     -       dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
>     -       dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
>     -       dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
>     -       dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
>     -       dev_priv->rps.cur_delay = 0;
>     +       parse_rp_state_cap(dev_priv, rp_state_cap);
>
>              /* disable the counters and set deterministic thresholds */
>              I915_WRITE(GEN6_RC_CONTROL, 0);
>     --
>     1.8.5.3
>
>     _______________________________________________
>     Intel-gfx mailing list
>     Intel-gfx@lists.freedesktop.org <mailto:Intel-gfx@lists.freedesktop.org>
>     http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

Looks fine
Reviewed-by: Deepak S <deepak.s@intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6acb429..ae59bd9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3184,6 +3184,17 @@  static void gen6_enable_rps_interrupts(struct drm_device *dev)
 	I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
 }
 
+static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
+{
+	/* In units of 50MHz */
+	dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
+	dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
+	dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
+	dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
+	dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
+	dev_priv->rps.cur_delay = 0;
+}
+
 static void gen8_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3202,6 +3213,7 @@  static void gen8_enable_rps(struct drm_device *dev)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+	parse_rp_state_cap(dev_priv, rp_state_cap);
 
 	/* 2b: Program RC6 thresholds.*/
 	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
@@ -3288,13 +3300,7 @@  static void gen6_enable_rps(struct drm_device *dev)
 	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 	gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 
-	/* In units of 50MHz */
-	dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
-	dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
-	dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
-	dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
-	dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
-	dev_priv->rps.cur_delay = 0;
+	parse_rp_state_cap(dev_priv, rp_state_cap);
 
 	/* disable the counters and set deterministic thresholds */
 	I915_WRITE(GEN6_RC_CONTROL, 0);