From patchwork Thu Jan 30 19:00:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3558911 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8088A9F2E9 for ; Thu, 30 Jan 2014 19:00:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D5FE7201C0 for ; Thu, 30 Jan 2014 19:00:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 768F0201BF for ; Thu, 30 Jan 2014 19:00:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 38B9A1028DF; Thu, 30 Jan 2014 11:00:44 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id E9E69101A44 for ; Thu, 30 Jan 2014 11:00:39 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 30 Jan 2014 11:00:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,751,1384329600"; d="scan'208";a="475347072" Received: from unknown (HELO ironside.amr.corp.intel.com) ([10.255.13.53]) by orsmga002.jf.intel.com with ESMTP; 30 Jan 2014 11:00:36 -0800 From: Ben Widawsky To: Intel GFX Date: Thu, 30 Jan 2014 11:00:35 -0800 Message-Id: <1391108435-1261-1-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.8.5.3 Cc: "David E. Box" , Ben Widawsky , Kristen Carlson Accardi , Ben Widawsky Subject: [Intel-gfx] [PATCH] [RFT] drm/i915: Ensure a context is loaded before RC6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP RC6 works a lot like HW contexts in that when the GPU enters RC6 it saves away the state to a context, and loads it upon wake. It's to be somewhat expected that BIOS will not set up valid GPU state. As a result, if loading bad state can cause the GPU to get angry, it would make sense then that we need to load state first. There are two ways in which we can do this: 1. Create 3d state in the driver, load it up, then enable RC6. 1b. Reuse a known good state, and just bind objects where needed. Then enable RC6 2. Hold off enabling RC6 until userspace has had a chance to complete batches. This patch is a bad hack. It suffers two flaws. The first is, if the driver is loaded, but a batch is not submitted/completed, we'll never enter rc6. The other is, it expects userspace to submit a batch with 3d state first. Both of these things are not actual flaws for most users. Technically, this tactic is required for all platforms, though I am not certain we've seen real failures. Cc: David E. Box Cc: Kristen Carlson Accardi Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem.c | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 4 ---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 08331e1..83847fc 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2482,6 +2482,7 @@ void i915_gem_reset(struct drm_device *dev) void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) { + static bool rc6_enabled = false; uint32_t seqno; if (list_empty(&ring->request_list)) @@ -2505,6 +2506,11 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) if (!i915_seqno_passed(seqno, obj->last_read_seqno)) break; + if (unlikely(!rc6_enabled) && ring->id == RCS) { + intel_enable_gt_powersave(ring->dev); + rc6_enabled = true; + } + i915_gem_object_move_to_inactive(obj); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4d4a0d9..990819a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10982,10 +10982,6 @@ void intel_modeset_init_hw(struct drm_device *dev) intel_init_clock_gating(dev); intel_reset_dpio(dev); - - mutex_lock(&dev->struct_mutex); - intel_enable_gt_powersave(dev); - mutex_unlock(&dev->struct_mutex); } void intel_modeset_suspend_hw(struct drm_device *dev)