| Message ID | 1391195447-8744-11-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Feb 01, 2014 at 12:40:46AM +0530, sagar.a.kamble@intel.com wrote: > From: Sagar Kamble <sagar.a.kamble@intel.com> > > Primary planes support 180 degree rotation. Expose the feature > through rotation drm property. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> > Tested-by: Sagar Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 54 ++++++++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > 3 files changed, 55 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 57906c5..d3000c4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3553,6 +3553,7 @@ > #define DISPPLANE_NO_LINE_DOUBLE 0 > #define DISPPLANE_STEREO_POLARITY_FIRST 0 > #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) > +#define DISPPLANE_ROTATE_180 (1<<15) > #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ > #define DISPPLANE_TILED (1<<10) > #define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 4d4a0d9..483de59 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2037,6 +2037,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > unsigned long linear_offset; > u32 dspcntr; > u32 reg; > + int pixel_size; > > switch (plane) { > case 0: > @@ -2047,6 +2048,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > return -EINVAL; > } > > + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); > intel_fb = to_intel_framebuffer(fb); > obj = intel_fb->obj; > > @@ -2054,6 +2056,8 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > dspcntr = I915_READ(reg); > /* Mask out pixel format bits in case we change it */ > dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; > + dspcntr &= ~DISPPLANE_ROTATE_180; > + > switch (fb->pixel_format) { > case DRM_FORMAT_C8: > dspcntr |= DISPPLANE_8BPP; > @@ -2095,8 +2099,6 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > if (IS_G4X(dev)) > dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; > > - I915_WRITE(reg, dspcntr); > - > linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > > if (INTEL_INFO(dev)->gen >= 4) { > @@ -2109,6 +2111,17 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > intel_crtc->dspaddr_offset = linear_offset; > } > > + if (intel_crtc->rotation == BIT(DRM_ROTATE_180)) { > + dspcntr |= DISPPLANE_ROTATE_180; > + > + x += (fb->width - 1); > + y += (fb->height - 1); > + linear_offset += (fb->height - 1) * fb->pitches[0] + > + fb->width * pixel_size; > + } This isn't quite right. We need something like: x += pipe_src_w - 1; y += pipe_src_h - 1; That suggests your tests don't check if panning works correctly when rotated. I was also going to say we need to do this before stashing the result into intel_crtc->dspaddr_offset on gen2/3, but it actually looks like rotation is a gen4+ feature, so this place looks OK for this code. You've also forgotten to add the rotation bits to ironlake_update_plane(). That one will need additional HSW/BDW checks I think. > + > + I915_WRITE(reg, dspcntr); > + > DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", > i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, > fb->pitches[0]); > @@ -8748,6 +8761,31 @@ free_work: > return ret; > } > > +static int intel_crtc_set_property(struct drm_crtc *crtc, > + struct drm_property *prop, > + uint64_t val) > +{ > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + uint64_t old_val; > + int ret = -ENOENT; > + > + if (prop == dev_priv->rotation_property) { > + /* exactly one rotation angle please */ > + if (hweight32(val & 0xf) != 1) > + return -EINVAL; > + > + old_val = intel_crtc->rotation; > + intel_crtc->rotation = val; > + ret = dev_priv->display.update_plane(crtc, crtc->fb, 0, 0); > + if (ret) > + intel_crtc->rotation = old_val; > + } > + > + return ret; > +} > + > static struct drm_crtc_helper_funcs intel_helper_funcs = { > .mode_set_base_atomic = intel_pipe_set_base_atomic, > .load_lut = intel_crtc_load_lut, > @@ -10160,6 +10198,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { > .set_config = intel_crtc_set_config, > .destroy = intel_crtc_destroy, > .page_flip = intel_crtc_page_flip, > + .set_property = intel_crtc_set_property > }; > > static void intel_cpu_pll_init(struct drm_device *dev) > @@ -10288,6 +10327,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > */ > intel_crtc->pipe = pipe; > intel_crtc->plane = pipe; > + intel_crtc->rotation = BIT(DRM_ROTATE_0); > if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { > DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); > intel_crtc->plane = !pipe; > @@ -10298,6 +10338,16 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; > dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; > > + if (!dev_priv->rotation_property) > + dev_priv->rotation_property = > + drm_mode_create_rotation_property(dev, > + BIT(DRM_ROTATE_0) | > + BIT(DRM_ROTATE_180)); > + if (dev_priv->rotation_property) > + drm_object_attach_property(&intel_crtc->base.base, > + dev_priv->rotation_property, > + intel_crtc->rotation); As I mentioned it looks like rotation is only supported starting from gen4. So we need to check for that here before we add the props. > + > drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); > } > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 7a79b8e..02dfdb6 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -331,6 +331,8 @@ struct intel_crtc { > struct drm_crtc base; > enum pipe pipe; > enum plane plane; > + unsigned int rotation; > + > u8 lut_r[256], lut_g[256], lut_b[256]; > /* > * Whether the crtc and the connected output pipeline is active. Implies > -- > 1.8.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Sat, Feb 01, 2014 at 12:40:46AM +0530, sagar.a.kamble@intel.com wrote: > From: Sagar Kamble <sagar.a.kamble@intel.com> > > Primary planes support 180 degree rotation. Expose the feature > through rotation drm property. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> > Tested-by: Sagar Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 54 ++++++++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > 3 files changed, 55 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 57906c5..d3000c4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3553,6 +3553,7 @@ > #define DISPPLANE_NO_LINE_DOUBLE 0 > #define DISPPLANE_STEREO_POLARITY_FIRST 0 > #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) > +#define DISPPLANE_ROTATE_180 (1<<15) > #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ > #define DISPPLANE_TILED (1<<10) > #define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 4d4a0d9..483de59 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2037,6 +2037,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > unsigned long linear_offset; > u32 dspcntr; > u32 reg; > + int pixel_size; > > switch (plane) { > case 0: > @@ -2047,6 +2048,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > return -EINVAL; > } > > + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); > intel_fb = to_intel_framebuffer(fb); > obj = intel_fb->obj; > > @@ -2054,6 +2056,8 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > dspcntr = I915_READ(reg); > /* Mask out pixel format bits in case we change it */ > dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; > + dspcntr &= ~DISPPLANE_ROTATE_180; > + > switch (fb->pixel_format) { > case DRM_FORMAT_C8: > dspcntr |= DISPPLANE_8BPP; > @@ -2095,8 +2099,6 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > if (IS_G4X(dev)) > dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; > > - I915_WRITE(reg, dspcntr); > - > linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > > if (INTEL_INFO(dev)->gen >= 4) { > @@ -2109,6 +2111,17 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, > intel_crtc->dspaddr_offset = linear_offset; > } > > + if (intel_crtc->rotation == BIT(DRM_ROTATE_180)) { > + dspcntr |= DISPPLANE_ROTATE_180; > + > + x += (fb->width - 1); > + y += (fb->height - 1); > + linear_offset += (fb->height - 1) * fb->pitches[0] + > + fb->width * pixel_size; > + } > + > + I915_WRITE(reg, dspcntr); > + > DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", > i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, > fb->pitches[0]); > @@ -8748,6 +8761,31 @@ free_work: > return ret; > } > > +static int intel_crtc_set_property(struct drm_crtc *crtc, > + struct drm_property *prop, > + uint64_t val) > +{ > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + uint64_t old_val; > + int ret = -ENOENT; > + > + if (prop == dev_priv->rotation_property) { > + /* exactly one rotation angle please */ > + if (hweight32(val & 0xf) != 1) > + return -EINVAL; > + > + old_val = intel_crtc->rotation; > + intel_crtc->rotation = val; Couple of other things we'd need to do here is check if the crtc is even active, since calling .update_plane() on an inactive crtc would oops. Also we need to wait for pending page flips to make sure we don't overtake them. Additionall the FBC code would need some rotation checks since FBC doesn't work with a rotated plane on certain generations. > + ret = dev_priv->display.update_plane(crtc, crtc->fb, 0, 0); > + if (ret) > + intel_crtc->rotation = old_val; > + } > + > + return ret; > +} > + > static struct drm_crtc_helper_funcs intel_helper_funcs = { > .mode_set_base_atomic = intel_pipe_set_base_atomic, > .load_lut = intel_crtc_load_lut, > @@ -10160,6 +10198,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { > .set_config = intel_crtc_set_config, > .destroy = intel_crtc_destroy, > .page_flip = intel_crtc_page_flip, > + .set_property = intel_crtc_set_property > }; > > static void intel_cpu_pll_init(struct drm_device *dev) > @@ -10288,6 +10327,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > */ > intel_crtc->pipe = pipe; > intel_crtc->plane = pipe; > + intel_crtc->rotation = BIT(DRM_ROTATE_0); > if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { > DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); > intel_crtc->plane = !pipe; > @@ -10298,6 +10338,16 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; > dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; > > + if (!dev_priv->rotation_property) > + dev_priv->rotation_property = > + drm_mode_create_rotation_property(dev, > + BIT(DRM_ROTATE_0) | > + BIT(DRM_ROTATE_180)); > + if (dev_priv->rotation_property) > + drm_object_attach_property(&intel_crtc->base.base, > + dev_priv->rotation_property, > + intel_crtc->rotation); > + > drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); > } > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 7a79b8e..02dfdb6 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -331,6 +331,8 @@ struct intel_crtc { > struct drm_crtc base; > enum pipe pipe; > enum plane plane; > + unsigned int rotation; > + > u8 lut_r[256], lut_g[256], lut_b[256]; > /* > * Whether the crtc and the connected output pipeline is active. Implies > -- > 1.8.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 57906c5..d3000c4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3553,6 +3553,7 @@ #define DISPPLANE_NO_LINE_DOUBLE 0 #define DISPPLANE_STEREO_POLARITY_FIRST 0 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_ROTATE_180 (1<<15) #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ #define DISPPLANE_TILED (1<<10) #define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4d4a0d9..483de59 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2037,6 +2037,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, unsigned long linear_offset; u32 dspcntr; u32 reg; + int pixel_size; switch (plane) { case 0: @@ -2047,6 +2048,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, return -EINVAL; } + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); intel_fb = to_intel_framebuffer(fb); obj = intel_fb->obj; @@ -2054,6 +2056,8 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, dspcntr = I915_READ(reg); /* Mask out pixel format bits in case we change it */ dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; + dspcntr &= ~DISPPLANE_ROTATE_180; + switch (fb->pixel_format) { case DRM_FORMAT_C8: dspcntr |= DISPPLANE_8BPP; @@ -2095,8 +2099,6 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, if (IS_G4X(dev)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; - I915_WRITE(reg, dspcntr); - linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); if (INTEL_INFO(dev)->gen >= 4) { @@ -2109,6 +2111,17 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, intel_crtc->dspaddr_offset = linear_offset; } + if (intel_crtc->rotation == BIT(DRM_ROTATE_180)) { + dspcntr |= DISPPLANE_ROTATE_180; + + x += (fb->width - 1); + y += (fb->height - 1); + linear_offset += (fb->height - 1) * fb->pitches[0] + + fb->width * pixel_size; + } + + I915_WRITE(reg, dspcntr); + DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, fb->pitches[0]); @@ -8748,6 +8761,31 @@ free_work: return ret; } +static int intel_crtc_set_property(struct drm_crtc *crtc, + struct drm_property *prop, + uint64_t val) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + uint64_t old_val; + int ret = -ENOENT; + + if (prop == dev_priv->rotation_property) { + /* exactly one rotation angle please */ + if (hweight32(val & 0xf) != 1) + return -EINVAL; + + old_val = intel_crtc->rotation; + intel_crtc->rotation = val; + ret = dev_priv->display.update_plane(crtc, crtc->fb, 0, 0); + if (ret) + intel_crtc->rotation = old_val; + } + + return ret; +} + static struct drm_crtc_helper_funcs intel_helper_funcs = { .mode_set_base_atomic = intel_pipe_set_base_atomic, .load_lut = intel_crtc_load_lut, @@ -10160,6 +10198,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { .set_config = intel_crtc_set_config, .destroy = intel_crtc_destroy, .page_flip = intel_crtc_page_flip, + .set_property = intel_crtc_set_property }; static void intel_cpu_pll_init(struct drm_device *dev) @@ -10288,6 +10327,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) */ intel_crtc->pipe = pipe; intel_crtc->plane = pipe; + intel_crtc->rotation = BIT(DRM_ROTATE_0); if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); intel_crtc->plane = !pipe; @@ -10298,6 +10338,16 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; + if (!dev_priv->rotation_property) + dev_priv->rotation_property = + drm_mode_create_rotation_property(dev, + BIT(DRM_ROTATE_0) | + BIT(DRM_ROTATE_180)); + if (dev_priv->rotation_property) + drm_object_attach_property(&intel_crtc->base.base, + dev_priv->rotation_property, + intel_crtc->rotation); + drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7a79b8e..02dfdb6 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -331,6 +331,8 @@ struct intel_crtc { struct drm_crtc base; enum pipe pipe; enum plane plane; + unsigned int rotation; + u8 lut_r[256], lut_g[256], lut_b[256]; /* * Whether the crtc and the connected output pipeline is active. Implies