From patchwork Fri Jan 31 21:42:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 3563831 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 19741C02DC for ; Fri, 31 Jan 2014 21:36:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EF48A20254 for ; Fri, 31 Jan 2014 21:36:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CF05620253 for ; Fri, 31 Jan 2014 21:36:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB5D8108289; Fri, 31 Jan 2014 13:36:39 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id BE3CEF9E09 for ; Fri, 31 Jan 2014 13:35:32 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 31 Jan 2014 13:31:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,759,1384329600"; d="scan'208";a="468004016" Received: from jeffdesk.fso.intel.com ([10.5.53.1]) by fmsmga001.fm.intel.com with ESMTP; 31 Jan 2014 13:35:31 -0800 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 31 Jan 2014 15:42:48 -0600 Message-Id: <1391204572-18888-2-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1391204572-18888-1-git-send-email-jeff.mcgee@intel.com> References: <1391204572-18888-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 1/5] drm/i915: Add RPS debugfs manual mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee RPS manual mode disables/ignores load-based inputs and allows render performance state to be controlled externally. The enabling of manual mode and setting of desired frequency is done through debugfs. i915_rps_manual: '0' - RPS controlled normally using load metrics. '1' - RPS controlled manually via i915_cur_freq writes. i915_cur_freq: u64 - Value is the current gpu frequency request in MHz. Writes accepted only if i915_rps_manual = 1. Supports Gen6+ except Valleyview and Broadwell. Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_debugfs.c | 111 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_irq.c | 6 ++ drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++-- 4 files changed, 156 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bc8707f..c6d4da0 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3322,6 +3322,115 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, i915_min_freq_get, i915_min_freq_set, "%llu\n"); +static int i915_cur_freq_get(void *data, u64 *val) +{ + struct drm_device *dev = data; + drm_i915_private_t *dev_priv = dev->dev_private; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + *val = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER; + + return 0; +} + +static int i915_cur_freq_set(void *data, u64 val) +{ + struct drm_device *dev = data; + struct drm_i915_private *dev_priv = dev->dev_private; + u64 freq = val; + int ret; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); + if (ret) + return ret; + + /* Must be in manual mode to guarantee setting will persist. */ + if (!dev_priv->rps.manual_mode) { + mutex_unlock(&dev_priv->rps.hw_lock); + return -EINVAL; + } + + do_div(val, GT_FREQUENCY_MULTIPLIER); + + if (val < dev_priv->rps.min_delay || val > dev_priv->rps.max_delay) { + mutex_unlock(&dev_priv->rps.hw_lock); + return -EINVAL; + } + + DRM_DEBUG_DRIVER("Setting current freq to %llu\n", freq); + + gen6_set_rps(dev, val); + + mutex_unlock(&dev_priv->rps.hw_lock); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_cur_freq_fops, + i915_cur_freq_get, i915_cur_freq_set, + "%llu\n"); + +static int i915_rps_manual_get(void *data, u64 *val) +{ + struct drm_device *dev = data; + drm_i915_private_t *dev_priv = dev->dev_private; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + *val = dev_priv->rps.manual_mode; + + return 0; +} + +static int i915_rps_manual_set(void *data, u64 val) +{ + struct drm_device *dev = data; + struct drm_i915_private *dev_priv = dev->dev_private; + int ret; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + DRM_DEBUG_DRIVER("Setting RPS mode to %s\n", + val ? "manual" : "normal"); + + ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); + if (ret) + return ret; + + gen6_set_rps_mode(dev, val); + + mutex_unlock(&dev_priv->rps.hw_lock); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rps_manual_fops, + i915_rps_manual_get, i915_rps_manual_set, + "%llu\n"); + static int i915_cache_sharing_get(void *data, u64 *val) { @@ -3496,6 +3605,8 @@ static const struct i915_debugfs_files { {"i915_wedged", &i915_wedged_fops}, {"i915_max_freq", &i915_max_freq_fops}, {"i915_min_freq", &i915_min_freq_fops}, + {"i915_cur_freq", &i915_cur_freq_fops}, + {"i915_rps_manual", &i915_rps_manual_fops}, {"i915_cache_sharing", &i915_cache_sharing_fops}, {"i915_ring_stop", &i915_ring_stop_fops}, {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fa37dfd..73fd646 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -968,6 +968,7 @@ struct intel_gen6_power_mgmt { int last_adj; enum { LOW_POWER, BETWEEN, HIGH_POWER } power; + bool manual_mode; bool enabled; struct delayed_work delayed_resume_work; @@ -2536,6 +2537,7 @@ extern bool intel_fbc_enabled(struct drm_device *dev); extern void intel_disable_fbc(struct drm_device *dev); extern bool ironlake_set_drps(struct drm_device *dev, u8 val); extern void intel_init_pch_refclk(struct drm_device *dev); +extern void gen6_set_rps_mode(struct drm_device *dev, bool manual); extern void gen6_set_rps(struct drm_device *dev, u8 val); extern void valleyview_set_rps(struct drm_device *dev, u8 val); extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b226ae6..7b04949 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1045,6 +1045,12 @@ static void gen6_pm_rps_work(struct work_struct *work) mutex_lock(&dev_priv->rps.hw_lock); + /* May have just entered manual mode. */ + if (dev_priv->rps.manual_mode) { + mutex_unlock(&dev_priv->rps.hw_lock); + return; + } + adj = dev_priv->rps.last_adj; if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { if (adj > 0) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3c79b63..cfdf5f0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3014,7 +3014,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val) if (val == dev_priv->rps.cur_delay) return; - gen6_set_rps_thresholds(dev_priv, val); + if (!dev_priv->rps.manual_mode) + gen6_set_rps_thresholds(dev_priv, val); if (IS_HASWELL(dev)) I915_WRITE(GEN6_RPNSWREQ, @@ -3038,12 +3039,44 @@ void gen6_set_rps(struct drm_device *dev, u8 val) trace_intel_gpu_freq_change(val * 50); } +void gen6_set_rps_mode(struct drm_device *dev, bool manual) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u8 delay; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) { + DRM_DEBUG_DRIVER("RPS mode change not supported\n"); + return; + } + + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + + dev_priv->rps.manual_mode = manual; + + /* Manual mode disables/ignores load-based inputs and allows render + * performance state to be controlled externally. */ + if (manual) { + I915_WRITE(GEN6_RP_CONTROL, + GEN6_RP_MEDIA_HW_NORMAL_MODE); + delay = (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8; + } else { + /* Force a reset */ + dev_priv->rps.power = HIGH_POWER; + dev_priv->rps.cur_delay = 0; + delay = dev_priv->rps.min_delay; + } + + gen6_set_rps(dev, delay); +} + void gen6_rps_idle(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; mutex_lock(&dev_priv->rps.hw_lock); - if (dev_priv->rps.enabled) { + if (dev_priv->rps.enabled && !dev_priv->rps.manual_mode) { if (IS_VALLEYVIEW(dev)) valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay); else @@ -3058,7 +3091,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv) struct drm_device *dev = dev_priv->dev; mutex_lock(&dev_priv->rps.hw_lock); - if (dev_priv->rps.enabled) { + if (dev_priv->rps.enabled && !dev_priv->rps.manual_mode) { if (IS_VALLEYVIEW(dev)) valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay); else @@ -3366,8 +3399,7 @@ static void gen6_enable_rps(struct drm_device *dev) DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); } - dev_priv->rps.power = HIGH_POWER; /* force a reset */ - gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); + gen6_set_rps_mode(dev, dev_priv->rps.manual_mode); gen6_enable_rps_interrupts(dev);