From patchwork Fri Jan 31 21:42:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 3563821 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3E3A39F381 for ; Fri, 31 Jan 2014 21:36:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 614FF20254 for ; Fri, 31 Jan 2014 21:36:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7A07920253 for ; Fri, 31 Jan 2014 21:36:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC3D510827F; Fri, 31 Jan 2014 13:36:33 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 23AB2FA4A7 for ; Fri, 31 Jan 2014 13:35:33 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 31 Jan 2014 13:31:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,759,1384329600"; d="scan'208";a="468004019" Received: from jeffdesk.fso.intel.com ([10.5.53.1]) by fmsmga001.fm.intel.com with ESMTP; 31 Jan 2014 13:35:31 -0800 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 31 Jan 2014 15:42:49 -0600 Message-Id: <1391204572-18888-3-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1391204572-18888-1-git-send-email-jeff.mcgee@intel.com> References: <1391204572-18888-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Add RC6 debugfs disabling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee i915_rc6_disable: '0' - RC6 states used normally per device and settings. '1' - RC6 states explicitly disabled. Supports Gen6+ except Valleyview and Broadwell. Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_debugfs.c | 49 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 5 ++++ drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++++++++++--- 3 files changed, 81 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c6d4da0..a51c357 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3431,6 +3431,54 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_rps_manual_fops, i915_rps_manual_get, i915_rps_manual_set, "%llu\n"); +static int i915_rc6_disable_get(void *data, u64 *val) +{ + struct drm_device *dev = data; + drm_i915_private_t *dev_priv = dev->dev_private; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + *val = dev_priv->rps.rc6_disable; + + return 0; +} + +static int i915_rc6_disable_set(void *data, u64 val) +{ + struct drm_device *dev = data; + struct drm_i915_private *dev_priv = dev->dev_private; + int ret; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) + return -ENODEV; + + flush_delayed_work(&dev_priv->rps.delayed_resume_work); + + DRM_DEBUG_DRIVER("Setting RC6 disable %s\n", + val ? "true" : "false"); + + ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); + if (ret) + return ret; + + gen6_set_rc6_mode(dev, val); + + mutex_unlock(&dev_priv->rps.hw_lock); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_rc6_disable_fops, + i915_rc6_disable_get, i915_rc6_disable_set, + "%llu\n"); + static int i915_cache_sharing_get(void *data, u64 *val) { @@ -3607,6 +3655,7 @@ static const struct i915_debugfs_files { {"i915_min_freq", &i915_min_freq_fops}, {"i915_cur_freq", &i915_cur_freq_fops}, {"i915_rps_manual", &i915_rps_manual_fops}, + {"i915_rc6_disable", &i915_rc6_disable_fops}, {"i915_cache_sharing", &i915_cache_sharing_fops}, {"i915_ring_stop", &i915_ring_stop_fops}, {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 73fd646..9893451 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -970,6 +970,10 @@ struct intel_gen6_power_mgmt { bool manual_mode; bool enabled; + + u32 rc6_mask; + bool rc6_disable; + struct delayed_work delayed_resume_work; /* @@ -2537,6 +2541,7 @@ extern bool intel_fbc_enabled(struct drm_device *dev); extern void intel_disable_fbc(struct drm_device *dev); extern bool ironlake_set_drps(struct drm_device *dev, u8 val); extern void intel_init_pch_refclk(struct drm_device *dev); +extern void gen6_set_rc6_mode(struct drm_device *dev, bool disable); extern void gen6_set_rps_mode(struct drm_device *dev, bool manual); extern void gen6_set_rps(struct drm_device *dev, u8 val); extern void valleyview_set_rps(struct drm_device *dev, u8 val); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index cfdf5f0..6478116 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3071,6 +3071,30 @@ void gen6_set_rps_mode(struct drm_device *dev, bool manual) gen6_set_rps(dev, delay); } +void gen6_set_rc6_mode(struct drm_device *dev, bool disable) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if ((INTEL_INFO(dev)->gen < 6) || + IS_VALLEYVIEW(dev) || + IS_BROADWELL(dev)) { + DRM_DEBUG_DRIVER("RC6 disable not supported\n"); + return; + } + + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + + dev_priv->rps.rc6_disable = disable; + + if (disable) + I915_WRITE(GEN6_RC_CONTROL, 0); + else + I915_WRITE(GEN6_RC_CONTROL, + dev_priv->rps.rc6_mask | + GEN6_RC_CTL_EI_MODE(1) | + GEN6_RC_CTL_HW_ENABLE); +} + void gen6_rps_idle(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; @@ -3376,10 +3400,9 @@ static void gen6_enable_rps(struct drm_device *dev) intel_print_rc6_info(dev, rc6_mask); - I915_WRITE(GEN6_RC_CONTROL, - rc6_mask | - GEN6_RC_CTL_EI_MODE(1) | - GEN6_RC_CTL_HW_ENABLE); + dev_priv->rps.rc6_mask = rc6_mask; + + gen6_set_rc6_mode(dev, dev_priv->rps.rc6_disable); /* Power down if completely idle for over 50ms */ I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);