From patchwork Fri Jan 31 21:42:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 3563851 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BB661C02DC for ; Fri, 31 Jan 2014 21:36:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C43E320253 for ; Fri, 31 Jan 2014 21:36:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C03CA20255 for ; Fri, 31 Jan 2014 21:36:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B3B310EA6C; Fri, 31 Jan 2014 13:36:45 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 9BE1810827A for ; Fri, 31 Jan 2014 13:35:33 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 31 Jan 2014 13:31:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,759,1384329600"; d="scan'208";a="468004034" Received: from jeffdesk.fso.intel.com ([10.5.53.1]) by fmsmga001.fm.intel.com with ESMTP; 31 Jan 2014 13:35:32 -0800 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 31 Jan 2014 15:42:52 -0600 Message-Id: <1391204572-18888-6-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1391204572-18888-1-git-send-email-jeff.mcgee@intel.com> References: <1391204572-18888-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Add CxSR debugfs disabling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee i915_sr_disable: '0' - CxSR enabled normally per device and settings. '1' - CxSR explicitly disabled. Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_debugfs.c | 43 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 47 +++++++++++++++++++++---------------- 3 files changed, 72 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 92f6213..cccb1bf 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1523,6 +1523,8 @@ static int i915_sr_status(struct seq_file *m, void *unused) sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; else if (IS_PINEVIEW(dev)) sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; + else if (IS_VALLEYVIEW(dev)) + sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; seq_printf(m, "self-refresh: %s\n", sr_enabled ? "enabled" : "disabled"); @@ -1530,6 +1532,46 @@ static int i915_sr_status(struct seq_file *m, void *unused) return 0; } +static int i915_sr_disable_get(void *data, u64 *val) +{ + struct drm_device *dev = data; + drm_i915_private_t *dev_priv = dev->dev_private; + + *val = dev_priv->sr_disable; + + return 0; +} + +static int i915_sr_disable_set(void *data, u64 val) +{ + struct drm_device *dev = data; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_crtc *crtc; + + if (dev_priv->sr_disable == (bool)val) + return 0; + + drm_modeset_lock_all(dev); + + DRM_DEBUG_DRIVER("Setting CxSR disable %s\n", + val ? "true" : "false"); + + dev_priv->sr_disable = (bool)val; + + /* Reset enabled crtc to force CxSR state update */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) + if (crtc->enabled) + intel_crtc_restore_mode(crtc); + + drm_modeset_unlock_all(dev); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_sr_disable_fops, + i915_sr_disable_get, i915_sr_disable_set, + "%llu\n"); + static int i915_emon_status(struct seq_file *m, void *unused) { struct drm_info_node *node = (struct drm_info_node *) m->private; @@ -3753,6 +3795,7 @@ static const struct i915_debugfs_files { {"i915_rc6_disable", &i915_rc6_disable_fops}, {"i915_ips_disable", &i915_ips_disable_fops}, {"i915_fbc_disable", &i915_fbc_disable_fops}, + {"i915_sr_disable", &i915_sr_disable_fops}, {"i915_cache_sharing", &i915_cache_sharing_fops}, {"i915_ring_stop", &i915_ring_stop_fops}, {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 18b2849..6d7dae2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1537,6 +1537,8 @@ typedef struct drm_i915_private { bool ips_disable; + bool sr_disable; + struct i915_power_domains power_domains; struct i915_psr psr; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a8605fc..93e1c60 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1041,7 +1041,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) } crtc = single_enabled_crtc(dev); - if (crtc) { + if (crtc && !dev_priv->sr_disable) { const struct drm_display_mode *adjusted_mode; int pixel_size = crtc->fb->bits_per_pixel / 8; int clock; @@ -1335,6 +1335,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc) enabled |= 1 << PIPE_B; if (single_plane_enabled(enabled) && + !dev_priv->sr_disable && g4x_compute_srwm(dev, ffs(enabled) - 1, sr_latency_ns, &valleyview_wm_info, @@ -1392,6 +1393,7 @@ static void g4x_update_wm(struct drm_crtc *crtc) enabled |= 1 << PIPE_B; if (single_plane_enabled(enabled) && + !dev_priv->sr_disable && g4x_compute_srwm(dev, ffs(enabled) - 1, sr_latency_ns, &g4x_wm_info, @@ -1433,7 +1435,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) /* Calc sr entries for one plane configs */ crtc = single_enabled_crtc(dev); - if (crtc) { + if (crtc && !dev_priv->sr_disable) { /* self-refresh has much higher latency */ static const int sr_latency_ns = 12000; const struct drm_display_mode *adjusted_mode = @@ -1603,7 +1605,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) I915_WRITE(FW_BLC2, fwater_hi); if (HAS_FW_BLC(dev)) { - if (enabled) { + if (enabled && !dev_priv->sr_disable) { if (IS_I945G(dev) || IS_I945GM(dev)) I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); @@ -2279,12 +2281,34 @@ static void ilk_compute_wm_results(struct drm_device *dev, enum intel_ddb_partitioning partitioning, struct ilk_wm_values *results) { + struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc; int level, wm_lp; results->enable_fbc_wm = merged->fbc_wm_enabled; results->partitioning = partitioning; + /* LP0 register values */ + list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { + enum pipe pipe = intel_crtc->pipe; + const struct intel_wm_level *r = + &intel_crtc->wm.active.wm[0]; + + if (WARN_ON(!r->enable)) + continue; + + results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; + + results->wm_pipe[pipe] = + (r->pri_val << WM0_PIPE_PLANE_SHIFT) | + (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | + r->cur_val; + } + + /* Leave LP1+ registers zeroed if self-refresh is not to be used */ + if (dev_priv->sr_disable) + return; + /* LP1+ register values */ for (wm_lp = 1; wm_lp <= 3; wm_lp++) { const struct intel_wm_level *r; @@ -2313,23 +2337,6 @@ static void ilk_compute_wm_results(struct drm_device *dev, } else results->wm_lp_spr[wm_lp - 1] = r->spr_val; } - - /* LP0 register values */ - list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { - enum pipe pipe = intel_crtc->pipe; - const struct intel_wm_level *r = - &intel_crtc->wm.active.wm[0]; - - if (WARN_ON(!r->enable)) - continue; - - results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; - - results->wm_pipe[pipe] = - (r->pri_val << WM0_PIPE_PLANE_SHIFT) | - (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | - r->cur_val; - } } /* Find the result with the highest level enabled. Check for enable_fbc_wm in