From patchwork Tue Feb 11 20:20:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3631381 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CE3179F2D6 for ; Tue, 11 Feb 2014 20:21:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E37902020A for ; Tue, 11 Feb 2014 20:21:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B7D42201FE for ; Tue, 11 Feb 2014 20:21:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CC39FAAF9; Tue, 11 Feb 2014 12:21:09 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EE4E1FAAF9 for ; Tue, 11 Feb 2014 12:21:06 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 11 Feb 2014 12:16:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.95,827,1384329600"; d="scan'208";a="453741340" Received: from unknown (HELO ironside.amr.corp.intel.com) ([10.255.12.87]) by orsmga001.jf.intel.com with ESMTP; 11 Feb 2014 12:20:43 -0800 From: Ben Widawsky To: Intel GFX Date: Tue, 11 Feb 2014 12:20:42 -0800 Message-Id: <1392150042-18837-1-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.8.5.4 In-Reply-To: <1391025333-31587-5-git-send-email-benjamin.widawsky@intel.com> References: <1391025333-31587-5-git-send-email-benjamin.widawsky@intel.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH] [v2] drm/i915: Make semaphore updates more precise X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With the ring mask we now have an easy way to know the number of rings in the system, and therefore can accurately predict the number of dwords to emit for semaphore signalling. This was not possible (easily) previously. There should be no functional impact, simply fewer instructions emitted. While we're here, simply do the round up to 2 instead of the fancier rounding we did before, which rounding up per mbox, ie 4. This also allows us to drop the unnecessary MI_NOOP, so not really 4, 3. v2: Use 3 dwords instead of 4 (Ville) Do the proper calculation to get the number of dwords to emit (Ville) Conditionally set .sync_to when semaphores are enabled (Ville) Signed-off-by: Ben Widawsky Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ringbuffer.c | 55 ++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 70f7190..483684f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -635,24 +635,19 @@ static void render_ring_cleanup(struct intel_ring_buffer *ring) static int gen6_signal(struct intel_ring_buffer *signaller, unsigned int num_dwords) { +#define MBOX_UPDATE_DWORDS 3 struct drm_device *dev = signaller->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_ring_buffer *useless; - int i, ret; + int i, ret, num_rings; - /* NB: In order to be able to do semaphore MBOX updates for varying - * number of rings, it's easiest if we round up each individual update - * to a multiple of 2 (since ring updates must always be a multiple of - * 2) even though the actual update only requires 3 dwords. - */ -#define MBOX_UPDATE_DWORDS 4 - if (i915_semaphore_is_enabled(dev)) - num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); + num_rings = hweight_long(INTEL_INFO(dev)->ring_mask); + num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); +#undef MBOX_UPDATE_DWORDS ret = intel_ring_begin(signaller, num_dwords); if (ret) return ret; -#undef MBOX_UPDATE_DWORDS for_each_ring(useless, dev_priv, i) { u32 mbox_reg = signaller->semaphore.signal_mbox[i]; @@ -660,15 +655,13 @@ static int gen6_signal(struct intel_ring_buffer *signaller, intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit(signaller, mbox_reg); intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); - intel_ring_emit(signaller, MI_NOOP); - } else { - intel_ring_emit(signaller, MI_NOOP); - intel_ring_emit(signaller, MI_NOOP); - intel_ring_emit(signaller, MI_NOOP); - intel_ring_emit(signaller, MI_NOOP); } } + /* If num_dwords was rounded, make sure the tail pointer is correct */ + if (num_rings % 2 == 0) + intel_ring_emit(signaller, MI_NOOP); + return 0; } @@ -686,7 +679,11 @@ gen6_add_request(struct intel_ring_buffer *ring) { int ret; - ret = ring->semaphore.signal(ring, 4); + if (ring->semaphore.signal) + ret = ring->semaphore.signal(ring, 4); + else + ret = intel_ring_begin(ring, 4); + if (ret) return ret; @@ -1880,8 +1877,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; - ring->semaphore.sync_to = gen6_ring_sync; - ring->semaphore.signal = gen6_signal; + if (i915_semaphore_is_enabled(dev)) { + ring->semaphore.sync_to = gen6_ring_sync; + ring->semaphore.signal = gen6_signal; + } ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_INVALID; ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_RV; ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_RB; @@ -2057,8 +2056,10 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; } - ring->semaphore.sync_to = gen6_ring_sync; - ring->semaphore.signal = gen6_signal; + if (i915_semaphore_is_enabled(dev)) { + ring->semaphore.sync_to = gen6_ring_sync; + ring->semaphore.signal = gen6_signal; + } ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_VR; ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_INVALID; ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_VB; @@ -2115,8 +2116,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) ring->irq_put = gen6_ring_put_irq; ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; } - ring->semaphore.sync_to = gen6_ring_sync; - ring->semaphore.signal = gen6_signal; + if (i915_semaphore_is_enabled(dev)) { + ring->semaphore.signal = gen6_signal; + ring->semaphore.sync_to = gen6_ring_sync; + } ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_BR; ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_BV; ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_INVALID; @@ -2157,8 +2160,10 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) ring->irq_put = hsw_vebox_put_irq; ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; } - ring->semaphore.sync_to = gen6_ring_sync; - ring->semaphore.signal = gen6_signal; + if (i915_semaphore_is_enabled(dev)) { + ring->semaphore.sync_to = gen6_ring_sync; + ring->semaphore.signal = gen6_signal; + } ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_VER; ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_VEV; ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_VEB;