From patchwork Wed Feb 12 16:55:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 3639381 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 46A5CBF13A for ; Wed, 12 Feb 2014 17:17:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A6E62018E for ; Wed, 12 Feb 2014 17:16:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3A6C120160 for ; Wed, 12 Feb 2014 17:16:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7B92FAB0D; Wed, 12 Feb 2014 09:16:55 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id A38D9FAB0D for ; Wed, 12 Feb 2014 09:16:53 -0800 (PST) Received: by mail-ee0-f49.google.com with SMTP id d17so4510257eek.36 for ; Wed, 12 Feb 2014 09:16:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=5JeivCfYzD0Ayeyh60DKJyxeVENn6d9h/YCZ4h1lc7g=; b=bRxmrUtZn8YdhInqSwTKck6Cb00+NyuqYupCKrCj2xyHpvlgnwAsZh/7p9gDbx3XIb 3w62STNL5IQ49sEgL+dZkQloU6WVo/ZIZbNOlJx1BGKU8YcEZa8jAQZA0RuPozL2G74l YM3vYtKMA6pPySJrR3GvMJUOcmMjbPJvqLw7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=5JeivCfYzD0Ayeyh60DKJyxeVENn6d9h/YCZ4h1lc7g=; b=Rn/KYgs5BDarmjo2ZjjCLhimCfxEpIMtlN4NiMdo0R5bQE+NLmuNBoQetxJ5DJEW7Z zUM7jCz0DnPcGeJEac8wZ2F20IvJ6SmU8FYdCXvs5igiLLi6nkGJNuV8gsr0tLwyO54z rb+xsL41h0rYfQMZRiLa0goDjdEoynSPJmF7NNRk7845BLe6TzAmQgJScsfprMEQsxr6 gxu2dt827A/WyHQhNvRP7Q3SNtKHAhX7BQr2Rj2HkIHd20Gs75gyYpyhkO0K+DWtCoyC q4oKisI3s5MFNrSwbYHmsxJULFGp83PlZNgWWF6BHz0UnfuzdPjW17pZ9QQuT5GQbh3w kArg== X-Gm-Message-State: ALoCoQnkKBzA4GQ8TTQ/7ce3Fg017K79gzJgbJTs6OBrFaUo88vmoA6fKp36XG2wpJuU4XLMSn7s X-Received: by 10.15.33.193 with SMTP id c41mr4504868eev.79.1392225411325; Wed, 12 Feb 2014 09:16:51 -0800 (PST) Received: from wespe.ffwll.local (84-73-67-144.dclient.hispeed.ch. [84.73.67.144]) by mx.google.com with ESMTPSA id m1sm83096542een.7.2014.02.12.09.16.49 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Feb 2014 09:16:50 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 12 Feb 2014 17:55:36 +0100 Message-Id: <1392224136-19620-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1392222066-11154-1-git-send-email-daniel.vetter@ffwll.ch> References: <1392222066-11154-1-git-send-email-daniel.vetter@ffwll.ch> MIME-Version: 1.0 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: Some polish for the new pipestat_irq_handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Just a bit of polish which I hope will help me with massaging some internal patches to use Imre's reworked pipestat handling: - Don't check for underrun reporting or enable pipestat interrupts twice. - Frob the comments a bit. - Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We only have one place which does this, so better to make it explicit. v2: Ville noticed that I've broken the logic a bit with trying to avoid checking whether we're interested in a given pipe twice. push the PIPESTAT read down after we've computed the mask of interesting bits first to avoid that duplication properly. Cc: Imre Deak Cc: Ville Syrjälä Signed-off-by: Daniel Vetter Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/i915_irq.c | 36 +++++++++++++++++++++++++----------- drivers/gpu/drm/i915/i915_reg.h | 4 ---- 2 files changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 386a640b7c92..a45ed67407bd 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1559,25 +1559,39 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) spin_lock(&dev_priv->irq_lock); for_each_pipe(pipe) { int reg; - u32 mask; - - if (!dev_priv->pipestat_irq_mask[pipe] && - !__cpu_fifo_underrun_reporting_enabled(dev, pipe)) - continue; - - reg = PIPESTAT(pipe); - pipe_stats[pipe] = I915_READ(reg); + u32 mask, iir_bit; /* - * Clear the PIPE*STAT regs before the IIR + * PIPESTAT bits get signalled even when the interrupt is + * disabled with the mask bits, and some of the status bits do + * not generate interrupts at all (like the underrun bit). Hence + * we need to be careful that we only handle what we want to + * handle. */ mask = PIPESTAT_INT_ENABLE_MASK; if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) mask |= PIPE_FIFO_UNDERRUN_STATUS; - if (iir & I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe)) + + switch (pipe) { + case PIPE_A: + iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; + break; + case PIPE_B: + iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; + break; + } + if (iir & iir_bit) mask |= dev_priv->pipestat_irq_mask[pipe]; - pipe_stats[pipe] &= mask; + if (!mask) + continue; + + reg = PIPESTAT(pipe); + pipe_stats[pipe] = I915_READ(reg) & mask; + + /* + * Clear the PIPE*STAT regs before the IIR + */ if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | PIPESTAT_INT_STATUS_MASK)) I915_WRITE(reg, pipe_stats[pipe]); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 645221270c34..8344541bbb93 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -997,10 +997,6 @@ #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe) \ - ((pipe) == PIPE_A ? I915_DISPLAY_PIPE_A_EVENT_INTERRUPT : \ - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) - #define I915_DEBUG_INTERRUPT (1<<2) #define I915_USER_INTERRUPT (1<<1) #define I915_ASLE_INTERRUPT (1<<0)