From patchwork Wed Feb 12 20:26:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 3640721 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8E8EA9F38E for ; Wed, 12 Feb 2014 20:26:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 956C22012B for ; Wed, 12 Feb 2014 20:26:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A8E6C20136 for ; Wed, 12 Feb 2014 20:26:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DEE4FB01A; Wed, 12 Feb 2014 12:26:42 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from alt-proxy58.mail.unifiedlayer.com (alt-proxy58.mail.unifiedlayer.com [173.254.1.16]) by gabe.freedesktop.org (Postfix) with SMTP id 1FA7CFB013 for ; Wed, 12 Feb 2014 12:26:36 -0800 (PST) Received: (qmail 13362 invoked by uid 0); 12 Feb 2014 20:26:34 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy6.mail.unifiedlayer.com with SMTP; 12 Feb 2014 20:26:34 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=s/1xNJfhx+xxsge8zhC07AcsG3wa+mHIHoyxSErU/eM=; b=l2USItj5WUgosHPHVtjiAcLiF4dqRMBVTeuiDOfYAWKVLi0g5U1Gl1xmVyGIvGYIlODEmTApTboIqiaTBH87kwDPsAA4zp4WFvFwzHmiFzI0HdabaMSdhTYHkct9LjUq; Received: from [67.161.37.189] (port=45280 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (UNKNOWN:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1WDgO9-0004u7-QJ for intel-gfx@lists.freedesktop.org; Wed, 12 Feb 2014 13:26:33 -0700 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Feb 2014 12:26:28 -0800 Message-Id: <1392236789-2740-5-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392236789-2740-1-git-send-email-jbarnes@virtuousgeek.org> References: <1392236789-2740-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 5/6] drm/i915: get_plane_config support for ILK+ v2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This should allow BIOS fb inheritance to work on ILK+ machines too. v2: handle tiled BIOS fbs (Kristian) split out common bits (Jesse) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 67 ++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ce22d05..134586b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6585,6 +6585,71 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, } } +static void ironlake_get_plane_config(struct intel_crtc *crtc, + struct intel_plane_config *plane_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 val, base, offset; + int pipe = crtc->pipe, plane = crtc->plane; + int fourcc, pixel_format; + int aligned_height; + + plane_config->fb = kzalloc(sizeof(*plane_config->fb), GFP_KERNEL); + if (!plane_config->fb) { + DRM_DEBUG_KMS("failed to alloc fb\n"); + return; + } + + val = I915_READ(DSPCNTR(plane)); + + if (INTEL_INFO(dev)->gen >= 4) + if (val & DISPPLANE_TILED) + plane_config->tiled = true; + + pixel_format = val & DISPPLANE_PIXFORMAT_MASK; + fourcc = intel_format_to_fourcc(pixel_format); + plane_config->fb->base.pixel_format = fourcc; + plane_config->fb->base.bits_per_pixel = + drm_format_plane_cpp(fourcc, 0) * 8; + + base = I915_READ(DSPSURF(plane)) & 0xfffff000; + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { + offset = I915_READ(DSPOFFSET(plane)); + } else { + if (plane_config->tiled) + offset = I915_READ(DSPTILEOFF(plane)); + else + offset = I915_READ(DSPLINOFF(plane)); + } + + val = I915_READ(PIPESRC(pipe)); + plane_config->fb->base.width = ((val >> 16) & 0xfff) + 1; + plane_config->fb->base.height = ((val >> 0) & 0xfff) + 1; + + val = I915_READ(DSPSTRIDE(pipe)); + plane_config->fb->base.pitches[0] = val & 0xffffff80; + + aligned_height = intel_align_height(dev, plane_config->fb->base.height, + plane_config->tiled); + + plane_config->size = ALIGN(plane_config->fb->base.pitches[0] * + aligned_height, PAGE_SIZE); + + DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + pipe, plane, plane_config->fb->base.width, + plane_config->fb->base.height, + plane_config->fb->base.bits_per_pixel, base, + plane_config->fb->base.pitches[0], + plane_config->size); + + /* + * If the fb is shared between multiple heads, we'll just get the + * first one. + */ + intel_alloc_plane_obj(dev, plane_config, base, fourcc); +} + static bool ironlake_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config) { @@ -10867,6 +10932,7 @@ static void intel_init_display(struct drm_device *dev) if (HAS_DDI(dev)) { dev_priv->display.get_pipe_config = haswell_get_pipe_config; + dev_priv->display.get_plane_config = ironlake_get_plane_config; dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; dev_priv->display.crtc_enable = haswell_crtc_enable; dev_priv->display.crtc_disable = haswell_crtc_disable; @@ -10874,6 +10940,7 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.update_plane = ironlake_update_plane; } else if (HAS_PCH_SPLIT(dev)) { dev_priv->display.get_pipe_config = ironlake_get_pipe_config; + dev_priv->display.get_plane_config = ironlake_get_plane_config; dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; dev_priv->display.crtc_enable = ironlake_crtc_enable; dev_priv->display.crtc_disable = ironlake_crtc_disable;