| Message ID | 1392674540-10915-4-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 18 Feb 2014 00:02:04 +0200 Imre Deak <imre.deak@intel.com> wrote: > These functions will be needed by the valleyview specific power well > update functionality added in an upcoming patch, so move them earlier. > > No functional change. > > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 140 +++++++++++++++++------------------ > 1 file changed, 70 insertions(+), 70 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 17c2033..fa50f6e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3953,6 +3953,76 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) > I915_WRITE(BCLRPAT(crtc->pipe), 0); > } > > +#define for_each_power_domain(domain, mask) \ > + for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > + if ((1 << (domain)) & (mask)) > + > +static unsigned long get_pipe_power_domains(struct drm_device *dev, > + enum pipe pipe, bool pfit_enabled) > +{ > + unsigned long mask; > + enum transcoder transcoder; > + > + transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); > + > + mask = BIT(POWER_DOMAIN_PIPE(pipe)); > + mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); > + if (pfit_enabled) > + mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); > + > + return mask; > +} > + > +void intel_display_set_init_power(struct drm_i915_private *dev_priv, > + bool enable) > +{ > + if (dev_priv->power_domains.init_power_on == enable) > + return; > + > + if (enable) > + intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); > + else > + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); > + > + dev_priv->power_domains.init_power_on = enable; > +} > + > +static void modeset_update_power_wells(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; > + struct intel_crtc *crtc; > + > + /* > + * First get all needed power domains, then put all unneeded, to avoid > + * any unnecessary toggling of the power wells. > + */ > + list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { > + enum intel_display_power_domain domain; > + > + if (!crtc->base.enabled) > + continue; > + > + pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, > + crtc->pipe, > + crtc->config.pch_pfit.enabled); > + > + for_each_power_domain(domain, pipe_domains[crtc->pipe]) > + intel_display_power_get(dev_priv, domain); > + } > + > + list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { > + enum intel_display_power_domain domain; > + > + for_each_power_domain(domain, crtc->enabled_power_domains) > + intel_display_power_put(dev_priv, domain); > + > + crtc->enabled_power_domains = pipe_domains[crtc->pipe]; > + } > + > + intel_display_set_init_power(dev_priv, false); > +} > + > int valleyview_get_vco(struct drm_i915_private *dev_priv) > { > int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; > @@ -6838,76 +6908,6 @@ static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) > mutex_unlock(&dev_priv->pc8.lock); > } > > -#define for_each_power_domain(domain, mask) \ > - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ > - if ((1 << (domain)) & (mask)) > - > -static unsigned long get_pipe_power_domains(struct drm_device *dev, > - enum pipe pipe, bool pfit_enabled) > -{ > - unsigned long mask; > - enum transcoder transcoder; > - > - transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); > - > - mask = BIT(POWER_DOMAIN_PIPE(pipe)); > - mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); > - if (pfit_enabled) > - mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); > - > - return mask; > -} > - > -void intel_display_set_init_power(struct drm_i915_private *dev_priv, > - bool enable) > -{ > - if (dev_priv->power_domains.init_power_on == enable) > - return; > - > - if (enable) > - intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); > - else > - intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); > - > - dev_priv->power_domains.init_power_on = enable; > -} > - > -static void modeset_update_power_wells(struct drm_device *dev) > -{ > - struct drm_i915_private *dev_priv = dev->dev_private; > - unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; > - struct intel_crtc *crtc; > - > - /* > - * First get all needed power domains, then put all unneeded, to avoid > - * any unnecessary toggling of the power wells. > - */ > - list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { > - enum intel_display_power_domain domain; > - > - if (!crtc->base.enabled) > - continue; > - > - pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, > - crtc->pipe, > - crtc->config.pch_pfit.enabled); > - > - for_each_power_domain(domain, pipe_domains[crtc->pipe]) > - intel_display_power_get(dev_priv, domain); > - } > - > - list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { > - enum intel_display_power_domain domain; > - > - for_each_power_domain(domain, crtc->enabled_power_domains) > - intel_display_power_put(dev_priv, domain); > - > - crtc->enabled_power_domains = pipe_domains[crtc->pipe]; > - } > - > - intel_display_set_init_power(dev_priv, false); > -} > - > static void haswell_modeset_global_resources(struct drm_device *dev) > { > modeset_update_power_wells(dev); Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 17c2033..fa50f6e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3953,6 +3953,76 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) I915_WRITE(BCLRPAT(crtc->pipe), 0); } +#define for_each_power_domain(domain, mask) \ + for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ + if ((1 << (domain)) & (mask)) + +static unsigned long get_pipe_power_domains(struct drm_device *dev, + enum pipe pipe, bool pfit_enabled) +{ + unsigned long mask; + enum transcoder transcoder; + + transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); + + mask = BIT(POWER_DOMAIN_PIPE(pipe)); + mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); + if (pfit_enabled) + mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); + + return mask; +} + +void intel_display_set_init_power(struct drm_i915_private *dev_priv, + bool enable) +{ + if (dev_priv->power_domains.init_power_on == enable) + return; + + if (enable) + intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); + else + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); + + dev_priv->power_domains.init_power_on = enable; +} + +static void modeset_update_power_wells(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; + struct intel_crtc *crtc; + + /* + * First get all needed power domains, then put all unneeded, to avoid + * any unnecessary toggling of the power wells. + */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { + enum intel_display_power_domain domain; + + if (!crtc->base.enabled) + continue; + + pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, + crtc->pipe, + crtc->config.pch_pfit.enabled); + + for_each_power_domain(domain, pipe_domains[crtc->pipe]) + intel_display_power_get(dev_priv, domain); + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { + enum intel_display_power_domain domain; + + for_each_power_domain(domain, crtc->enabled_power_domains) + intel_display_power_put(dev_priv, domain); + + crtc->enabled_power_domains = pipe_domains[crtc->pipe]; + } + + intel_display_set_init_power(dev_priv, false); +} + int valleyview_get_vco(struct drm_i915_private *dev_priv) { int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; @@ -6838,76 +6908,6 @@ static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) mutex_unlock(&dev_priv->pc8.lock); } -#define for_each_power_domain(domain, mask) \ - for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ - if ((1 << (domain)) & (mask)) - -static unsigned long get_pipe_power_domains(struct drm_device *dev, - enum pipe pipe, bool pfit_enabled) -{ - unsigned long mask; - enum transcoder transcoder; - - transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); - - mask = BIT(POWER_DOMAIN_PIPE(pipe)); - mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); - if (pfit_enabled) - mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); - - return mask; -} - -void intel_display_set_init_power(struct drm_i915_private *dev_priv, - bool enable) -{ - if (dev_priv->power_domains.init_power_on == enable) - return; - - if (enable) - intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); - else - intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); - - dev_priv->power_domains.init_power_on = enable; -} - -static void modeset_update_power_wells(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; - struct intel_crtc *crtc; - - /* - * First get all needed power domains, then put all unneeded, to avoid - * any unnecessary toggling of the power wells. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { - enum intel_display_power_domain domain; - - if (!crtc->base.enabled) - continue; - - pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, - crtc->pipe, - crtc->config.pch_pfit.enabled); - - for_each_power_domain(domain, pipe_domains[crtc->pipe]) - intel_display_power_get(dev_priv, domain); - } - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { - enum intel_display_power_domain domain; - - for_each_power_domain(domain, crtc->enabled_power_domains) - intel_display_power_put(dev_priv, domain); - - crtc->enabled_power_domains = pipe_domains[crtc->pipe]; - } - - intel_display_set_init_power(dev_priv, false); -} - static void haswell_modeset_global_resources(struct drm_device *dev) { modeset_update_power_wells(dev);
These functions will be needed by the valleyview specific power well update functionality added in an upcoming patch, so move them earlier. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 140 +++++++++++++++++------------------ 1 file changed, 70 insertions(+), 70 deletions(-)