From patchwork Tue Feb 18 03:01:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3666991 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 95DA89F1EE for ; Tue, 18 Feb 2014 03:02:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 25C5D20107 for ; Tue, 18 Feb 2014 03:02:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 238AB20109 for ; Tue, 18 Feb 2014 03:02:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 81449FA956; Mon, 17 Feb 2014 19:02:31 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 65F46FA938 for ; Mon, 17 Feb 2014 19:02:03 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 17 Feb 2014 19:02:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,499,1389772800"; d="scan'208";a="484967311" Received: from unknown (HELO ironside.amr.corp.intel.com) ([10.255.13.201]) by orsmga002.jf.intel.com with ESMTP; 17 Feb 2014 19:02:02 -0800 From: Ben Widawsky To: Intel GFX Date: Mon, 17 Feb 2014 19:01:48 -0800 Message-Id: <1392692512-2268-8-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.8.5.5 In-Reply-To: <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> References: <1390969547-1018-2-git-send-email-benjamin.widawsky@intel.com> <1392692512-2268-1-git-send-email-benjamin.widawsky@intel.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 07/11] drm/i915/bdw: Extract rp_state_caps logic X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We have a need for duplicated parsing of the RP_STATE_CAPS register (and the setting of the associated fields). To reuse some code, we can extract the function into a simple helper. This patch also addresses the fact that we missed doing this for gen8, something we should have done anyway. This could be two patches, one to extract, and one to add gen8, but it's trivial enough that I think one is fine. I will accept a request to split it. Please notice the fix addressed by v2 below. Valleyview is left untouched because it is different. v2: Logically rebased on top of commit dd0a1aa19bd3d7203e58157b84cea78bbac605ac Author: Jeff McGee Date: Tue Feb 4 11:32:31 2014 -0600 drm/i915: Restore rps/rc6 on reset Note with the above change the fix for gen8 is also handled (which was not the case in Jeff's original patch). Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_pm.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4fe9a94..ac8419d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3245,6 +3245,25 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev) I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs); } +static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap) +{ + + /* In units of 50MHz */ + dev_priv->rps.nominal_freq = (rp_state_cap >> 16) & 0xff; + dev_priv->rps.min_freq_hardlimit = (rp_state_cap >> 8) & 0xff; + dev_priv->rps.max_freq_hardlimit = (rp_state_cap >> 0) & 0xff; + dev_priv->rps.max_freq_overclock = dev_priv->rps.max_freq_hardlimit; + dev_priv->rps.nominal_freq = dev_priv->rps.min_freq_hardlimit; + dev_priv->rps.cur_freq = 0; + + /* Preserve min/max settings in case of re-init */ + if (dev_priv->rps.max_freq_softlimit == 0) + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq_hardlimit; + + if (dev_priv->rps.min_freq_softlimit == 0) + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq_hardlimit; +} + static void gen8_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -3263,6 +3282,7 @@ static void gen8_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, 0); rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); + parse_rp_state_cap(dev_priv, rp_state_cap); /* 2b: Program RC6 thresholds.*/ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); @@ -3351,20 +3371,7 @@ static void gen6_enable_rps(struct drm_device *dev) rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); - /* In units of 50MHz */ - dev_priv->rps.nominal_freq = (rp_state_cap >> 16) & 0xff; - dev_priv->rps.min_freq_hardlimit = (rp_state_cap >> 8) & 0xff; - dev_priv->rps.max_freq_hardlimit = (rp_state_cap >> 0) & 0xff; - dev_priv->rps.max_freq_overclock = dev_priv->rps.max_freq_hardlimit; - dev_priv->rps.nominal_freq = dev_priv->rps.min_freq_hardlimit; - dev_priv->rps.cur_freq = 0; - - /* Preserve min/max settings in case of re-init */ - if (dev_priv->rps.max_freq_softlimit == 0) - dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq_hardlimit; - - if (dev_priv->rps.min_freq_softlimit == 0) - dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq_hardlimit; + parse_rp_state_cap(dev_priv, rp_state_cap); /* disable the counters and set deterministic thresholds */ I915_WRITE(GEN6_RC_CONTROL, 0);