@@ -408,6 +408,7 @@ struct intel_crtc_config;
struct intel_crtc;
struct intel_limit;
struct dpll;
+struct intel_crtc_wm_config;
struct drm_i915_display_funcs {
bool (*fbc_enabled)(struct drm_device *dev);
@@ -438,6 +439,10 @@ struct drm_i915_display_funcs {
struct drm_crtc *crtc,
uint32_t sprite_width, int pixel_size,
bool enable, bool scaled);
+ void (*program_wm_pre)(struct drm_crtc *crtc,
+ const struct intel_crtc_wm_config *config);
+ void (*program_wm_post)(struct drm_crtc *crtc,
+ const struct intel_crtc_wm_config *config);
void (*modeset_global_resources)(struct drm_device *dev);
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -338,6 +338,13 @@ struct intel_pipe_wm {
bool sprites_scaled;
};
+struct intel_crtc_wm_config {
+ /* target watermarks for the pipe */
+ struct intel_pipe_wm target;
+ /* intermediate watermarks for pending/active->target transition */
+ struct intel_pipe_wm intm;
+};
+
struct intel_crtc {
struct drm_crtc base;
enum pipe pipe;
@@ -2899,6 +2899,20 @@ void ilk_update_pipe_wm(struct drm_device *dev, enum pipe pipe)
spin_unlock(&intel_crtc->wm.lock);
}
+static void ilk_wm_cancel(struct intel_crtc *intel_crtc)
+{
+ struct drm_device *dev = intel_crtc->base.dev;
+
+ assert_spin_locked(&intel_crtc->wm.lock);
+
+ intel_crtc->wm.dirty = false;
+
+ if (intel_crtc->wm.vblank) {
+ drm_vblank_put(dev, intel_crtc->pipe);
+ intel_crtc->wm.vblank = false;
+ }
+}
+
static void ilk_update_sprite_wm(struct drm_plane *plane,
struct drm_crtc *crtc,
uint32_t sprite_width, int pixel_size,
@@ -3033,6 +3047,24 @@ void intel_update_sprite_watermarks(struct drm_plane *plane,
pixel_size, enabled, scaled);
}
+void intel_program_watermarks_pre(struct drm_crtc *crtc,
+ const struct intel_crtc_wm_config *config)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+
+ if (dev_priv->display.program_wm_pre)
+ dev_priv->display.program_wm_pre(crtc, config);
+}
+
+void intel_program_watermarks_post(struct drm_crtc *crtc,
+ const struct intel_crtc_wm_config *config)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+
+ if (dev_priv->display.program_wm_post)
+ dev_priv->display.program_wm_post(crtc, config);
+}
+
static struct drm_i915_gem_object *
intel_alloc_context_page(struct drm_device *dev)
{
@@ -5913,6 +5945,62 @@ void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
pm_runtime_disable(device);
}
+static void ilk_program_wm_pre(struct drm_crtc *crtc,
+ const struct intel_crtc_wm_config *config)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ mutex_lock(&dev_priv->wm.mutex);
+
+ spin_lock_irq(&intel_crtc->wm.lock);
+ ilk_wm_cancel(intel_crtc);
+ spin_unlock_irq(&intel_crtc->wm.lock);
+
+ /* pending update (if any) got cancelled */
+ intel_crtc->wm.pending = intel_crtc->wm.active;
+
+ if (!memcmp(&intel_crtc->wm.active, &config->intm, sizeof(config->intm)))
+ goto unlock;
+
+ intel_crtc->wm.active = config->intm;
+
+ /* use the most up to date watermarks for other pipes */
+ ilk_refresh_pending_watermarks(dev);
+
+ /* switch over to the intermediate watermarks */
+ ilk_program_watermarks(dev);
+
+ unlock:
+ mutex_unlock(&dev_priv->wm.mutex);
+}
+
+static void ilk_program_wm_post(struct drm_crtc *crtc,
+ const struct intel_crtc_wm_config *config)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ u32 vbl_count;
+
+ /*
+ * FIXME sample this inside the atomic section to avoid
+ * needlessly long periods w/ sub-par watermarks
+ */
+ vbl_count = dev->driver->get_vblank_counter(dev, intel_crtc->pipe);
+
+ mutex_lock(&dev_priv->wm.mutex);
+
+ /*
+ * We can switch over to the target
+ * watermarks after the next vblank.
+ */
+ ilk_setup_pending_watermarks(intel_crtc, &config->target, vbl_count);
+
+ mutex_unlock(&dev_priv->wm.mutex);
+}
+
/* Set up chip specific power management-related functions */
void intel_init_pm(struct drm_device *dev)
{
@@ -5960,6 +6048,8 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.update_wm = ilk_update_wm;
dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
+ dev_priv->display.program_wm_pre = ilk_program_wm_pre;
+ dev_priv->display.program_wm_post = ilk_program_wm_post;
} else {
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");