From patchwork Fri Mar 14 21:37:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 3837381 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B207A9F369 for ; Sat, 15 Mar 2014 13:37:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 16A0A20268 for ; Sat, 15 Mar 2014 13:37:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 371022026C for ; Sat, 15 Mar 2014 13:37:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 866BC8907F; Sat, 15 Mar 2014 06:37:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org X-Greylist: delayed 9201 seconds by postgrey-1.34 at gabe; Sat, 15 Mar 2014 06:37:22 PDT Received: from gproxy4-pub.mail.unifiedlayer.com (gproxy4-pub.mail.unifiedlayer.com [69.89.23.142]) by gabe.freedesktop.org (Postfix) with SMTP id 30BDD8907D for ; Sat, 15 Mar 2014 06:37:22 -0700 (PDT) Received: (qmail 21656 invoked by uid 0); 14 Mar 2014 21:37:20 -0000 Received: from unknown (HELO cmgw2) (10.0.90.83) by gproxy4.mail.unifiedlayer.com with SMTP; 14 Mar 2014 21:37:20 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by cmgw2 with id dZdE1n0052UhLwi01ZdHXr; Fri, 14 Mar 2014 15:37:19 -0600 X-Authority-Analysis: v=2.1 cv=ar4hV0pV c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=29R-MprNGnAA:10 a=3ROhxo7VqVMA:10 a=IkcTkHD0fZMA:10 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=pGLkceISAAAA:8 a=aePraUh2IpSLIXO1VrYA:9 a=QEXdDO2ut3YA:10 a=MSl-tDqOz04A:10 a=rW6DTWptwo0A:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=sudhJWKZY/lkBgzAe5Wr5r8yBphaFFNkI0ye3oLSMhU=; b=Ks5cAz2Qz9RtZmcm2hXTgP49BfcQRJdeX6HZji2DuD/EbMuEFu1qhLNvIRmxn+GSrt10K+N9JWJhnN8UeNuJFhBC07Jt2KHn4+x+g20TlqwqtPYSiqYg6O4zLKYFlKrg; Received: from [67.161.37.189] (port=34980 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (UNKNOWN:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1WOZn0-0007tS-S9; Fri, 14 Mar 2014 15:37:14 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Mar 2014 14:37:09 -0700 Message-Id: <1394833031-4055-2-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1394833031-4055-1-git-send-email-jbarnes@virtuousgeek.org> References: <1394833031-4055-1-git-send-email-jbarnes@virtuousgeek.org> MIME-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 2/4] drm/i915: don't bother enabling swizzle bits on gen7+ v2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As of IVB, the memory controller does internal swizzling already, so we shouldn't need to enable these. Based on an earlier fix from Kristian. v2: preserve swizzling if BIOS had it set (Daniel) Reported-by: Kristian Høgsberg Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 6 ++++++ drivers/gpu/drm/i915/i915_gem_tiling.c | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c64f770..29cd977 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1508,6 +1508,7 @@ typedef struct drm_i915_private { struct intel_vbt_data vbt; bool bios_ssc; /* BIOS had SSC enabled at boot? */ + bool bios_swizzle; /* overlay */ struct intel_overlay *overlay; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 92b0b41..87e34bc 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4313,6 +4313,9 @@ void i915_gem_init_swizzling(struct drm_device *dev) dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; + if (INTEL_INFO(dev)->gen >= 7 && !dev_priv->bios_swizzle) + return; + I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_TILE_SURFACE_SWIZZLING); @@ -4454,6 +4457,9 @@ int i915_gem_init(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int ret; + if (I915_READ(DISP_ARB_CTL) & DISP_TILE_SURFACE_SWIZZLING) + dev_priv->bios_swizzle = true; + mutex_lock(&dev->struct_mutex); if (IS_VALLEYVIEW(dev)) { diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index eb99358..c6447de 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -91,7 +91,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - if (IS_VALLEYVIEW(dev)) { + if (INTEL_INFO(dev)->gen >= 7 && + !(I915_READ(TILECTL) & TILECTL_SWZCTL)) { swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; } else if (INTEL_INFO(dev)->gen >= 6) {