From patchwork Fri Mar 21 18:48:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3875961 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8B588BF540 for ; Fri, 21 Mar 2014 18:48:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 71B9620203 for ; Fri, 21 Mar 2014 18:48:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 97B8A20225 for ; Fri, 21 Mar 2014 18:48:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 153D26E400; Fri, 21 Mar 2014 11:48:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 80F646E3FE for ; Fri, 21 Mar 2014 11:48:30 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 21 Mar 2014 11:48:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,704,1389772800"; d="scan'208";a="504097509" Received: from unknown (HELO ironside.amr.corp.intel.com) ([10.255.12.224]) by fmsmga002.fm.intel.com with ESMTP; 21 Mar 2014 11:48:29 -0700 From: Ben Widawsky To: Intel GFX Date: Fri, 21 Mar 2014 11:48:16 -0700 Message-Id: <1395427701-13434-8-git-send-email-benjamin.widawsky@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1395427701-13434-1-git-send-email-benjamin.widawsky@linux.intel.com> References: <1395427701-13434-1-git-send-email-benjamin.widawsky@linux.intel.com> MIME-Version: 1.0 Cc: stable@vger.kernel.org Subject: [Intel-gfx] [PATCH 07/12] drm/i915: Add thread stall DOP clock gating workaround on Broadwell. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kenneth Graunke Ben and I believe this will be necessary on production hardware. Signed-off-by: Kenneth Graunke [danvet: Shuffle lines to group all ROW_CHICKEN writes and add a cautious comment that this might not be needed on production hw.] Reviewed-by: Ville Syrjälä Reviewed-by: Ben Widawsky Signed-off-by: Daniel Vetter [BDW 3.14 backport] Cc: stable@vger.kernel.org Signed-off-by: Ben Widawsky Conflicts: drivers/gpu/drm/i915/intel_pm.c --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cb9ff13..d9b2292 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5014,6 +5014,7 @@ #define GEN8_ROW_CHICKEN 0xe4f0 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) +#define STALL_DOP_GATING_DISABLE (1<<5) #define GEN7_ROW_CHICKEN2 0xe4f4 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a7e5669..2b82a6b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4713,9 +4713,12 @@ static void gen8_init_clock_gating(struct drm_device *dev) WARN(!i915_preliminary_hw_support, "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n"); + /* WaDisablePartialInstShootdown:bdw */ + /* WaDisableThreadStallDopClockGating:bdw */ I915_WRITE(GEN8_ROW_CHICKEN, - _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); + _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | + STALL_DOP_GATING_DISABLE)); I915_WRITE(HALF_SLICE_CHICKEN3, _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));