From patchwork Wed Mar 26 10:41:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenneth Graunke X-Patchwork-Id: 3892581 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 75304BF540 for ; Wed, 26 Mar 2014 10:41:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A46B62021F for ; Wed, 26 Mar 2014 10:41:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7E315201BA for ; Wed, 26 Mar 2014 10:41:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01CB389E7B; Wed, 26 Mar 2014 03:41:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from homiemail-a10.g.dreamhost.com (caiajhbdccac.dreamhost.com [208.97.132.202]) by gabe.freedesktop.org (Postfix) with ESMTP id 61C7A89E7B for ; Wed, 26 Mar 2014 03:41:13 -0700 (PDT) Received: from homiemail-a10.g.dreamhost.com (localhost [127.0.0.1]) by homiemail-a10.g.dreamhost.com (Postfix) with ESMTP id 9719B280077; Wed, 26 Mar 2014 03:41:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=whitecape.org; h=from:to :cc:subject:date:message-id:in-reply-to:references; s= whitecape.org; bh=utHnMMnhem7poowhX6vZOl2Brk4=; b=BBD5+J5i4NOFbK Q6urNOdx2vKdcq6HA5duWszC4HAGkRSq2MtiKq1Werg+Egk3MpEKdqxcUjgrdHgM XGUvm7P9FnUMZXxHrRYrM6BW2M2hzk8rGltmnkqhzKJoZbzRVexDEHQKrqgVpgFj DJSUdLkKuJiaifgdAr4kNOiEztSZY= Received: from vakarian.shinigami (unknown [50.126.105.238]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: kenneth@whitecape.org) by homiemail-a10.g.dreamhost.com (Postfix) with ESMTPSA id 361B1280076; Wed, 26 Mar 2014 03:41:11 -0700 (PDT) From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org Date: Wed, 26 Mar 2014 03:41:36 -0700 Message-Id: <1395830496-773-1-git-send-email-kenneth@whitecape.org> X-Mailer: git-send-email 1.9.0 In-Reply-To: <87wqfhgu3g.fsf@intel.com> References: <87wqfhgu3g.fsf@intel.com> Subject: [Intel-gfx] [PATCH v2] drm/i915: Add OACONTROL to the command parser register whitelist. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Mesa needs to be able to write OACONTROL in order to expose the Observability Architecture's performance counters via OpenGL. v2: Insert in proper sorted order (caught by Jani Nikula). Signed-off-by: Kenneth Graunke --- drivers/gpu/drm/i915/i915_cmd_parser.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 3 insertions(+) Sorry, totally missed that. Thanks for catching that, Jani. diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index bae7c2f..1cd8d3a 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -407,6 +407,7 @@ static const u32 gen7_render_regs[] = { REG64(CL_PRIMITIVES_COUNT), REG64(PS_INVOCATION_COUNT), REG64(PS_DEPTH_COUNT), + OACONTROL, REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9f9e2b7..0ebc20d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -427,6 +427,8 @@ /* There are the 4 64-bit counter registers, one for each stream output */ #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) +#define OACONTROL 0x2360 + #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \