From patchwork Fri Mar 28 21:29:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 3907591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B7D9ABF540 for ; Fri, 28 Mar 2014 21:30:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB0C92034F for ; Fri, 28 Mar 2014 21:30:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 08A392034C for ; Fri, 28 Mar 2014 21:30:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9FA9B6EDAC; Fri, 28 Mar 2014 14:30:01 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id E55DA6EDAC for ; Fri, 28 Mar 2014 14:29:59 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 28 Mar 2014 14:29:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,752,1389772800"; d="scan'208";a="509265431" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.65]) by fmsmga002.fm.intel.com with SMTP; 28 Mar 2014 14:29:39 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 28 Mar 2014 23:29:38 +0200 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Mar 2014 23:29:31 +0200 Message-Id: <1396042172-32495-3-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396042172-32495-1-git-send-email-ville.syrjala@linux.intel.com> References: <1396042172-32495-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Fix the interlace mode selection for gmch platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä PIPECONF_INTERLACE_W_FIELD_INDICATION is only meant to be used for sdvo since it implies a slightly weird vsync shift of htotal/2. For everything else we should use PIPECONF_INTERLACE_W_SYNC_SHIFT and let the value in the VSYNCSHIFT register take effect. The only exception is gen3 simply because VSYNCSHIFT didn't exist yet. Gen2 doesn't support interlaced modes at all, so we can drop the explicit gen2 checks. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a9a4f6a..3ab40e3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5543,13 +5543,13 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) } } - if (IS_VALLEYVIEW(dev) && - intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) - pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; - else if (!IS_GEN2(dev) && - intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) - pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; - else + if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { + if (INTEL_INFO(dev)->gen < 4 || + intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) + pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; + else + pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; + } else pipeconf |= PIPECONF_PROGRESSIVE; if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)