diff mbox

drm/i915: Use a macro to express the range of valid gens for reg_read

Message ID 1396261448-30300-1-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien March 31, 2014, 10:24 a.m. UTC
The reg_read whitelist has a gen bitmask to code the gens we're allowing
the register to be read on. Until now, it was a litteral, but we can be
a bit more expressive.

To ease the review, a small test program:

  $ cat bit-range.c
  #include <stdio.h>
  #include <stdint.h>

  #define U32_C(x)		x ## U
  #define GENMASK(h, l)		(((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
  #define GEN_RANGE(l, h)	GENMASK(h, l)

  int main(int argc, char **argv)
  {
	printf("0x%08x\n", GEN_RANGE(1, 1));
	printf("0x%08x\n", GEN_RANGE(1, 2));
	printf("0x%08x\n", GEN_RANGE(4, 4));
	printf("0x%08x\n", GEN_RANGE(4, 5));
	printf("0x%08x\n", GEN_RANGE(1, 31));
	printf("0x%08x\n", GEN_RANGE(4, 8));

	return 0;
  }
  $ ./bit-range
  0x00000002
  0x00000006
  0x00000010
  0x00000030
  0xfffffffe
  0x000001f0

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Comments

Jani Nikula March 31, 2014, 10:47 a.m. UTC | #1
On Mon, 31 Mar 2014, Damien Lespiau <damien.lespiau@intel.com> wrote:
> The reg_read whitelist has a gen bitmask to code the gens we're allowing
> the register to be read on. Until now, it was a litteral, but we can be
> a bit more expressive.

s/litteral/literal/

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> To ease the review, a small test program:
>
>   $ cat bit-range.c
>   #include <stdio.h>
>   #include <stdint.h>
>
>   #define U32_C(x)		x ## U
>   #define GENMASK(h, l)		(((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
>   #define GEN_RANGE(l, h)	GENMASK(h, l)
>
>   int main(int argc, char **argv)
>   {
> 	printf("0x%08x\n", GEN_RANGE(1, 1));
> 	printf("0x%08x\n", GEN_RANGE(1, 2));
> 	printf("0x%08x\n", GEN_RANGE(4, 4));
> 	printf("0x%08x\n", GEN_RANGE(4, 5));
> 	printf("0x%08x\n", GEN_RANGE(1, 31));
> 	printf("0x%08x\n", GEN_RANGE(4, 8));
>
> 	return 0;
>   }
>   $ ./bit-range
>   0x00000002
>   0x00000006
>   0x00000010
>   0x00000030
>   0xfffffffe
>   0x000001f0
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 823d699..e2aa964 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -860,12 +860,15 @@ void intel_uncore_fini(struct drm_device *dev)
>  	intel_uncore_forcewake_reset(dev, false);
>  }
>  
> +#define GEN_RANGE(l, h) GENMASK(h, l)
> +
>  static const struct register_whitelist {
>  	uint64_t offset;
>  	uint32_t size;
> -	uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
> +	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
> +	uint32_t gen_bitmask;
>  } whitelist[] = {
> -	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
> +	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) },
>  };
>  
>  int i915_reg_read_ioctl(struct drm_device *dev,
> -- 
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter March 31, 2014, 12:08 p.m. UTC | #2
On Mon, Mar 31, 2014 at 01:47:12PM +0300, Jani Nikula wrote:
> On Mon, 31 Mar 2014, Damien Lespiau <damien.lespiau@intel.com> wrote:
> > The reg_read whitelist has a gen bitmask to code the gens we're allowing
> > the register to be read on. Until now, it was a litteral, but we can be
> > a bit more expressive.
> 
> s/litteral/literal/

Fixed.

> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Queued for -next, thanks for the patch.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 823d699..e2aa964 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -860,12 +860,15 @@  void intel_uncore_fini(struct drm_device *dev)
 	intel_uncore_forcewake_reset(dev, false);
 }
 
+#define GEN_RANGE(l, h) GENMASK(h, l)
+
 static const struct register_whitelist {
 	uint64_t offset;
 	uint32_t size;
-	uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
+	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
+	uint32_t gen_bitmask;
 } whitelist[] = {
-	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
+	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) },
 };
 
 int i915_reg_read_ioctl(struct drm_device *dev,