From patchwork Sun Apr 6 19:54:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3943691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B05F1BFF02 for ; Sun, 6 Apr 2014 19:54:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 79C982021A for ; Sun, 6 Apr 2014 19:54:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4D69220200 for ; Sun, 6 Apr 2014 19:54:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5BFDB6E456; Sun, 6 Apr 2014 12:54:20 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CEAD6E456 for ; Sun, 6 Apr 2014 12:54:19 -0700 (PDT) Received: by mail.bwidawsk.net (Postfix, from userid 5001) id A40424A6CC; Sun, 6 Apr 2014 12:54:18 -0700 (PDT) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from ironside.amr.corp.intel.com (unknown [198.0.49.227]) by mail.bwidawsk.net (Postfix) with ESMTPSA id 36C734A6AC for ; Sun, 6 Apr 2014 12:54:13 -0700 (PDT) From: Ben Widawsky To: Intel GFX Date: Sun, 6 Apr 2014 12:54:09 -0700 Message-Id: <1396814050-10338-1-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Reorganize uncore_init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Right now we have two separate tables for doing platform specific init. With one table it's a lot clearer exactly where new things need to go (which I'll be doing in a subsequent patch). There is no intended functional change here. Only cleanup. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_uncore.c | 134 ++++++++++++++++++++---------------- 1 file changed, 74 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 76dc185..e206c41 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -739,6 +739,47 @@ __gen4_write(64) #undef REG_WRITE_FOOTER #undef REG_WRITE_HEADER + +static void ivybridge_setup_forcewake(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 ecobus; + + /* IVB configs may use multi-threaded forcewake */ + + /* A small trick here - if the bios hasn't configured MT forcewake, and + * if the device is in RC6, then force_wake_mt_get will not wake the + * device and the ECOBUS read will return zero. Which will be + * (correctly) interpreted by the test below as MT forcewake being + * disabled. + */ + mutex_lock(&dev->struct_mutex); + __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); + ecobus = __raw_i915_read32(dev_priv, ECOBUS); + __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); + mutex_unlock(&dev->struct_mutex); + + if (ecobus & FORCEWAKE_MT_ENABLE) { + dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; + dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; + } else { + DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); + DRM_INFO("when using vblank-synced partial screen updates.\n"); + dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_get; + dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_put; + } +} + +#define gen6_setup_read_mmio(dev_priv) do { \ + (dev_priv)->uncore.funcs.mmio_readb = gen6_read8; \ + (dev_priv)->uncore.funcs.mmio_readw = gen6_read16; \ + (dev_priv)->uncore.funcs.mmio_readl = gen6_read32; \ + (dev_priv)->uncore.funcs.mmio_readq = gen6_read64; \ +} while (0) + +/* You can use this function to initialize gen specific function pointers + * that need to be initialized early. + */ void intel_uncore_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -748,87 +789,60 @@ void intel_uncore_init(struct drm_device *dev) intel_uncore_early_sanitize(dev); - if (IS_VALLEYVIEW(dev)) { - dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; - dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; - } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { + switch (INTEL_INFO(dev)->gen) { + case 8: dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; - } else if (IS_IVYBRIDGE(dev)) { - u32 ecobus; - - /* IVB configs may use multi-threaded forcewake */ - - /* A small trick here - if the bios hasn't configured - * MT forcewake, and if the device is in RC6, then - * force_wake_mt_get will not wake the device and the - * ECOBUS read will return zero. Which will be - * (correctly) interpreted by the test below as MT - * forcewake being disabled. - */ - mutex_lock(&dev->struct_mutex); - __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); - ecobus = __raw_i915_read32(dev_priv, ECOBUS); - __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); - mutex_unlock(&dev->struct_mutex); - - if (ecobus & FORCEWAKE_MT_ENABLE) { - dev_priv->uncore.funcs.force_wake_get = - __gen7_gt_force_wake_mt_get; - dev_priv->uncore.funcs.force_wake_put = - __gen7_gt_force_wake_mt_put; - } else { - DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); - DRM_INFO("when using vblank-synced partial screen updates.\n"); - dev_priv->uncore.funcs.force_wake_get = - __gen6_gt_force_wake_get; - dev_priv->uncore.funcs.force_wake_put = - __gen6_gt_force_wake_put; - } - } else if (IS_GEN6(dev)) { - dev_priv->uncore.funcs.force_wake_get = - __gen6_gt_force_wake_get; - dev_priv->uncore.funcs.force_wake_put = - __gen6_gt_force_wake_put; - } - switch (INTEL_INFO(dev)->gen) { - default: + gen6_setup_read_mmio(dev_priv); dev_priv->uncore.funcs.mmio_writeb = gen8_write8; dev_priv->uncore.funcs.mmio_writew = gen8_write16; dev_priv->uncore.funcs.mmio_writel = gen8_write32; dev_priv->uncore.funcs.mmio_writeq = gen8_write64; - dev_priv->uncore.funcs.mmio_readb = gen6_read8; - dev_priv->uncore.funcs.mmio_readw = gen6_read16; - dev_priv->uncore.funcs.mmio_readl = gen6_read32; - dev_priv->uncore.funcs.mmio_readq = gen6_read64; + break; case 7: - case 6: if (IS_HASWELL(dev)) { + dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; + dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; + + gen6_setup_read_mmio(dev_priv); dev_priv->uncore.funcs.mmio_writeb = hsw_write8; dev_priv->uncore.funcs.mmio_writew = hsw_write16; dev_priv->uncore.funcs.mmio_writel = hsw_write32; dev_priv->uncore.funcs.mmio_writeq = hsw_write64; - } else { - dev_priv->uncore.funcs.mmio_writeb = gen6_write8; - dev_priv->uncore.funcs.mmio_writew = gen6_write16; - dev_priv->uncore.funcs.mmio_writel = gen6_write32; - dev_priv->uncore.funcs.mmio_writeq = gen6_write64; - } + } else if (IS_VALLEYVIEW(dev)) { + dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; + dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; - if (IS_VALLEYVIEW(dev)) { + gen6_setup_read_mmio(dev_priv); dev_priv->uncore.funcs.mmio_readb = vlv_read8; dev_priv->uncore.funcs.mmio_readw = vlv_read16; dev_priv->uncore.funcs.mmio_readl = vlv_read32; dev_priv->uncore.funcs.mmio_readq = vlv_read64; - } else { - dev_priv->uncore.funcs.mmio_readb = gen6_read8; - dev_priv->uncore.funcs.mmio_readw = gen6_read16; - dev_priv->uncore.funcs.mmio_readl = gen6_read32; - dev_priv->uncore.funcs.mmio_readq = gen6_read64; + } else if (IS_IVYBRIDGE(dev)) { + ivybridge_setup_forcewake(dev); + BUG_ON(!dev_priv->uncore.funcs.force_wake_get); + BUG_ON(!dev_priv->uncore.funcs.force_wake_put); + + gen6_setup_read_mmio(dev_priv); + dev_priv->uncore.funcs.mmio_writeb = gen6_write8; + dev_priv->uncore.funcs.mmio_writew = gen6_write16; + dev_priv->uncore.funcs.mmio_writel = gen6_write32; + dev_priv->uncore.funcs.mmio_writeq = gen6_write64; } break; + case 6: + dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_get; + dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_put; + + gen6_setup_read_mmio(dev_priv); + dev_priv->uncore.funcs.mmio_writeb = gen6_write8; + dev_priv->uncore.funcs.mmio_writew = gen6_write16; + dev_priv->uncore.funcs.mmio_writel = gen6_write32; + dev_priv->uncore.funcs.mmio_writeq = gen6_write64; + + break; case 5: dev_priv->uncore.funcs.mmio_writeb = gen5_write8; dev_priv->uncore.funcs.mmio_writew = gen5_write16;