From patchwork Thu Apr 10 07:04:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 3959981 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8BD0B9F336 for ; Thu, 10 Apr 2014 07:04:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BEB2320629 for ; Thu, 10 Apr 2014 07:04:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D46E720444 for ; Thu, 10 Apr 2014 07:04:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 650756EC09; Thu, 10 Apr 2014 00:04:54 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f50.google.com (mail-ee0-f50.google.com [74.125.83.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 27F8E6EC09 for ; Thu, 10 Apr 2014 00:04:53 -0700 (PDT) Received: by mail-ee0-f50.google.com with SMTP id c13so2601247eek.37 for ; Thu, 10 Apr 2014 00:04:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id; bh=dI3Zqkx8zD+IEW3JKTAnoqnvFoxGoLzO3Eo+vZcJIvc=; b=U614mQI3k2h8OXFQzxpSlDrRbIjTvSBdo6SVAAM7AX576lirajF8HXXNboddqYxMqz Z49/wFn6tr0B7plIs1Nhe4uB0Izps1r7WEP5RqJ13tunvdVrC/b51IEqLDcd/ziDyXcv eCp1J+euGJ4PdLL2a2R0FCwuXNaNpLXfFipt8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=dI3Zqkx8zD+IEW3JKTAnoqnvFoxGoLzO3Eo+vZcJIvc=; b=eSNA19423rLl8qzJ/AMa9+4yAgclmrJ1yx/R+a4YBjW6aLyEpj+z2T9OixYYN18XhD ghDl70Ms8cJetmGMllW2Gp9va85ZW9YWYbKJYiiNp94uW2frbcVef9hsgIkNR5h+5EL5 63Lpu+rH2/TpdmpIpUxnmvdlP6r2lBGww1L39bGrrI1Y00RgmLsQCSev6Xh1IwETDetN TB7+Icj0eo3HkUNEq3WrWlPd0jxbfz9n3p0oiggbC0zTJ5VAeWYc7m3hqxJ8LageXYzk wWRgbDP5SfEVq/5b0VvhsTvA41+zzCHmkyxUC+s+v6B38deAUxBzJzedJiaZ3BX/FTAB dGOw== X-Gm-Message-State: ALoCoQk11BU0VQw7z6sAw6r+Ouzh1wR77/QWNCdQEyuLx7t5hTeLZXJalC7LDHJib5ETB/iyouUY X-Received: by 10.15.53.69 with SMTP id q45mr18582434eew.22.1397113492309; Thu, 10 Apr 2014 00:04:52 -0700 (PDT) Received: from phenom.ffwll.local (84-73-67-144.dclient.hispeed.ch. [84.73.67.144]) by mx.google.com with ESMTPSA id x46sm7141015een.17.2014.04.10.00.04.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Apr 2014 00:04:51 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 10 Apr 2014 09:04:47 +0200 Message-Id: <1397113487-25717-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.5.2 Cc: Daniel Vetter , Paulo Zanoni Subject: [Intel-gfx] [PATCH] Revert "drm/i915: fix infinite loop at gen6_update_ring_freq" X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This reverts commit 4b28a1f3ef55a3b0b68dbab1fe6dbaf18e186710. This patch duct-tapes over some issue in the current bdw rps patches which must wait with enabling rc6/rps until the very first batch has been submitted by userspace. But those patches aren't merged yet, and for upstream we need to have an in-kernel emission of the very first batch. I shouldn't have merged this patch so let's revert it again. Also Imre noticed that even when rps is set up normally there's a small window (due to the 1s delay of the async rps init work) where we could runtime suspend already and blow up all over the place. Imre has a proper fix to block runtime pm until the rps init work has successfully completed. Cc: Paulo Zanoni Cc: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8531cf6e2774..dc7adadbb945 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3522,8 +3522,7 @@ void gen6_update_ring_freq(struct drm_device *dev) * to use for memory access. We do this by specifying the IA frequency * the PCU should use as a reference to determine the ring frequency. */ - for (gpu_freq = dev_priv->rps.max_freq_softlimit; - gpu_freq >= dev_priv->rps.min_freq_softlimit && gpu_freq != 0; + for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; gpu_freq--) { int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; unsigned int ia_freq = 0, ring_freq = 0;