From patchwork Tue Apr 15 16:41:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 3994131 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3A806BFF02 for ; Tue, 15 Apr 2014 16:41:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4DF66201D3 for ; Tue, 15 Apr 2014 16:41:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EF68220155 for ; Tue, 15 Apr 2014 16:41:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73A8C6E25A; Tue, 15 Apr 2014 09:41:33 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f179.google.com (mail-we0-f179.google.com [74.125.82.179]) by gabe.freedesktop.org (Postfix) with ESMTP id 84B596E25A for ; Tue, 15 Apr 2014 09:41:31 -0700 (PDT) Received: by mail-we0-f179.google.com with SMTP id x48so9513345wes.24 for ; Tue, 15 Apr 2014 09:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id; bh=2GYO32mRcqQXbLn4Axj/Rq+MneNlNEx3m7FQYUZF7xs=; b=j5POp4R6/cSkjHB20muN3as9Ccf43TcN0rIFvHBOeKyWEp8AF7g7nZTKcmTibu0suW xmsUV95zDqzEIygaSxrpelVNAeMLSZeWEcjZ4R7yEZMe2uHaNA2+GEhLL6fKJOqaRGEC RShFF67Cmi7VSf1t297t15eWoMhetqRS4Enl0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=2GYO32mRcqQXbLn4Axj/Rq+MneNlNEx3m7FQYUZF7xs=; b=Rvfv8eebTf+3cEV+cm2UyoSwY/sNoh/fB4qBVYgDtfqoNHfn9WQ5EsdkYSRT4qxd45 bgu9b6WW4NOODR5f2PIyxNXzJg7uPXGHVlX2gtJeZf5qeUPpxt5kXGOz20HwaM7L4iX8 ilsJ0SX582Rz2p+nVAVZpJT7A0R/wjJDJmjuxCfcVXzFwFrMalfUV2JwM8Ux9/3aqWp0 rBklJ2U4+R7apEMzHYjwec0RWsa8daSHVr+UpgcheDG06JcSzoZ2WfIaLXPH2maYEBRa +K1ge9VG72KN+Ywx/ZSLMAztswa24dEdd8LcFjKAJPSTPHH63LSfPQIf4AqXszAgjH9t xNmg== X-Gm-Message-State: ALoCoQnH92OBmW9JI/tqjVqaEmDqKZ73LxnVsiKx1PQxxxHUqhmnPyd2s0cEL3YGjcUkH8jlaTbP X-Received: by 10.14.4.69 with SMTP id 45mr3917993eei.66.1397580090204; Tue, 15 Apr 2014 09:41:30 -0700 (PDT) Received: from gina.ffwll.local (84-73-67-144.dclient.hispeed.ch. [84.73.67.144]) by mx.google.com with ESMTPSA id y7sm50396585eev.5.2014.04.15.09.41.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Apr 2014 09:41:29 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 15 Apr 2014 18:41:22 +0200 Message-Id: <1397580083-11558-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.4.rc3 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Don't vblank wait on ilk-ivb after pipe enable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Like on hsw/bdw the pipe isn't actually running yet at this point. This holds for both pch ports and the cpu edp port according to my testing on ilk, snb and ivb. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77297 Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1aae7361b7a5..e0310e3018ee 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1827,16 +1827,6 @@ static void intel_enable_pipe(struct intel_crtc *crtc) I915_WRITE(reg, val | PIPECONF_ENABLE); POSTING_READ(reg); - - /* - * There's no guarantee the pipe will really start running now. It - * depends on the Gen, the output type and the relative order between - * pipe and plane enabling. Avoid waiting on HSW+ since it's not - * necessary. - * TODO: audit the previous gens. - */ - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) - intel_wait_for_vblank(dev_priv->dev, pipe); } /** @@ -4461,7 +4451,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(intel_crtc); + intel_wait_for_vblank(dev_priv->dev, pipe); intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); + intel_enable_primary_hw_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); intel_crtc_update_cursor(crtc, true); @@ -4546,7 +4538,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(intel_crtc); + intel_wait_for_vblank(dev_priv->dev, pipe); intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); + intel_enable_primary_hw_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); /* The fixup needs to happen before cursor is enabled */