| Message ID | 1397616077-1125-2-git-send-email-yakui.zhao@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote: > Based on the hardware spec, the BDW GT3 has the different configuration > with the BDW GT1/GT2. So split the BDW device info definition. > This is to do the preparation for adding the Dual BSD rings on BDW GT3 machine. > > V1->V2: Follow Daniel's comment to pay attention to the stolen check for BDW > in kernel/early-quirks.c > > Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 26 ++++++++++++++++++++++++-- > include/drm/i915_pciids.h | 22 +++++++++++++++++----- > 2 files changed, 41 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 5d8250f..17fbbe5 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -279,6 +279,26 @@ static const struct intel_device_info intel_broadwell_m_info = { > GEN_DEFAULT_PIPEOFFSETS, > }; > > +static const struct intel_device_info intel_broadwell_gt3d_info = { > + .gen = 8, .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > +}; > + > +static const struct intel_device_info intel_broadwell_gt3m_info = { > + .gen = 8, .is_mobile = 1, .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > +}; > + > /* > * Make sure any device matches here are from most specific to most > * general. For example, since the Quanta match is based on the subsystem > @@ -311,8 +331,10 @@ static const struct intel_device_info intel_broadwell_m_info = { > INTEL_HSW_M_IDS(&intel_haswell_m_info), \ > INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ > INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ > - INTEL_BDW_M_IDS(&intel_broadwell_m_info), \ > - INTEL_BDW_D_IDS(&intel_broadwell_d_info) > + INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ > + INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ > + INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ > + INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info) > > static const struct pci_device_id pciidlist[] = { /* aka */ > INTEL_PCI_IDS, > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index 940ece4..24f3cad 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -223,14 +223,26 @@ > _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \ > _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */ > > -#define INTEL_BDW_M_IDS(info) \ > +#define INTEL_BDW_GT12M_IDS(info) \ > _INTEL_BDW_M_IDS(1, info), \ > - _INTEL_BDW_M_IDS(2, info), \ > - _INTEL_BDW_M_IDS(3, info) > + _INTEL_BDW_M_IDS(2, info) > > -#define INTEL_BDW_D_IDS(info) \ > +#define INTEL_BDW_GT12D_IDS(info) \ > _INTEL_BDW_D_IDS(1, info), \ > - _INTEL_BDW_D_IDS(2, info), \ > + _INTEL_BDW_D_IDS(2, info) > + > +#define INTEL_BDW_GT3M_IDS(info) \ > + _INTEL_BDW_M_IDS(3, info) > + > +#define INTEL_BDW_GT3D_IDS(info) \ > _INTEL_BDW_D_IDS(3, info) > > +#define INTEL_BDW_M_IDS(info) \ > + INTEL_BDW_GT12M_IDS(info), \ > + INTEL_BDW_GT3M_IDS(info) > + > +#define INTEL_BDW_D_IDS(info) \ > + INTEL_BDW_GT12D_IDS(info), \ > + INTEL_BDW_GT3D_IDS(info) > + > #endif /* _I915_PCIIDS_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5d8250f..17fbbe5 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -279,6 +279,26 @@ static const struct intel_device_info intel_broadwell_m_info = { GEN_DEFAULT_PIPEOFFSETS, }; +static const struct intel_device_info intel_broadwell_gt3d_info = { + .gen = 8, .num_pipes = 3, + .need_gfx_hws = 1, .has_hotplug = 1, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .has_llc = 1, + .has_ddi = 1, + .has_fbc = 1, + GEN_DEFAULT_PIPEOFFSETS, +}; + +static const struct intel_device_info intel_broadwell_gt3m_info = { + .gen = 8, .is_mobile = 1, .num_pipes = 3, + .need_gfx_hws = 1, .has_hotplug = 1, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .has_llc = 1, + .has_ddi = 1, + .has_fbc = 1, + GEN_DEFAULT_PIPEOFFSETS, +}; + /* * Make sure any device matches here are from most specific to most * general. For example, since the Quanta match is based on the subsystem @@ -311,8 +331,10 @@ static const struct intel_device_info intel_broadwell_m_info = { INTEL_HSW_M_IDS(&intel_haswell_m_info), \ INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ - INTEL_BDW_M_IDS(&intel_broadwell_m_info), \ - INTEL_BDW_D_IDS(&intel_broadwell_d_info) + INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ + INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ + INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ + INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info) static const struct pci_device_id pciidlist[] = { /* aka */ INTEL_PCI_IDS, diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 940ece4..24f3cad 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -223,14 +223,26 @@ _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \ _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */ -#define INTEL_BDW_M_IDS(info) \ +#define INTEL_BDW_GT12M_IDS(info) \ _INTEL_BDW_M_IDS(1, info), \ - _INTEL_BDW_M_IDS(2, info), \ - _INTEL_BDW_M_IDS(3, info) + _INTEL_BDW_M_IDS(2, info) -#define INTEL_BDW_D_IDS(info) \ +#define INTEL_BDW_GT12D_IDS(info) \ _INTEL_BDW_D_IDS(1, info), \ - _INTEL_BDW_D_IDS(2, info), \ + _INTEL_BDW_D_IDS(2, info) + +#define INTEL_BDW_GT3M_IDS(info) \ + _INTEL_BDW_M_IDS(3, info) + +#define INTEL_BDW_GT3D_IDS(info) \ _INTEL_BDW_D_IDS(3, info) +#define INTEL_BDW_M_IDS(info) \ + INTEL_BDW_GT12M_IDS(info), \ + INTEL_BDW_GT3M_IDS(info) + +#define INTEL_BDW_D_IDS(info) \ + INTEL_BDW_GT12D_IDS(info), \ + INTEL_BDW_GT3D_IDS(info) + #endif /* _I915_PCIIDS_H */
Based on the hardware spec, the BDW GT3 has the different configuration with the BDW GT1/GT2. So split the BDW device info definition. This is to do the preparation for adding the Dual BSD rings on BDW GT3 machine. V1->V2: Follow Daniel's comment to pay attention to the stolen check for BDW in kernel/early-quirks.c Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 26 ++++++++++++++++++++++++-- include/drm/i915_pciids.h | 22 +++++++++++++++++----- 2 files changed, 41 insertions(+), 7 deletions(-)