From patchwork Fri Apr 18 21:04:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 4018571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7C36DBFF02 for ; Fri, 18 Apr 2014 21:04:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8B9362038D for ; Fri, 18 Apr 2014 21:04:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AF9EF203AB for ; Fri, 18 Apr 2014 21:04:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3760C6ECF7; Fri, 18 Apr 2014 14:04:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f178.google.com (mail-pd0-f178.google.com [209.85.192.178]) by gabe.freedesktop.org (Postfix) with ESMTP id 673736ECFB for ; Fri, 18 Apr 2014 14:04:48 -0700 (PDT) Received: by mail-pd0-f178.google.com with SMTP id x10so1765820pdj.37 for ; Fri, 18 Apr 2014 14:04:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XUnbRmGB7Vx47Q1odf+vGlz56QorDnV/csp1JcUho9o=; b=d6Yhm4kVQ9jICcSUqvyXWSJTprJ7tCVNIkPzpwJcv82xN+t6MJI6h2LQD8JSRU8671 qnhlTi313pBXVKv0sBKK7yBxg5Qz/gpETZLj79oYGtI2d+7aWU3gKknwLj+98syTOxu2 ptT8YgbrkpA6FN8CGnAEmAqwQNJ0pHih+dr4ENXNwLp8s3zCMuRf0zlef/9z0ww5V531 S3fgZ8DSxGXriZKW6+TWg24eqBBrjFrLP9zDUyfT/cUpUKqY3NcMJBR6ZoUg9QJKerHw PhXlYWWX2VQ9ThTokE5nNxGlygfwlvlsGXZ5ADn9FWVA/P5PMlQ2v2Gg+XgfJzX61jMD 3Jkw== X-Received: by 10.66.142.170 with SMTP id rx10mr24192615pab.117.1397855088302; Fri, 18 Apr 2014 14:04:48 -0700 (PDT) Received: from localhost (jfdmzpr03-ext.jf.intel.com. [134.134.139.72]) by mx.google.com with ESMTPSA id it4sm61798474pbc.39.2014.04.18.14.04.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Apr 2014 14:04:47 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Fri, 18 Apr 2014 18:04:26 -0300 Message-Id: <1397855070-4480-11-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1397855070-4480-1-git-send-email-rodrigo.vivi@gmail.com> References: <1397855070-4480-1-git-send-email-rodrigo.vivi@gmail.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 10/14] drm/i915: Prevent context obj from being corrupted X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky While the context is not being used, we can make the PTEs invalid, so nothing can accidentally corrupt it. Systems tend to have a lot of trouble when the context gets corrupted. NOTE: This is a slightly different patch than what I posted to Bugzilla. References: https://bugs.freedesktop.org/show_bug.cgi?id=75724 Signed-off-by: Ben Widawsky Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_gem_context.c | 56 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 5474489..b913ef6 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -545,6 +545,58 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) return ctx; } +static void +_ctx_ptes(struct intel_ring_buffer *ring, + struct i915_hw_context *ctx, + bool valid) +{ + const size_t ptes = ctx->obj->base.size >> PAGE_SHIFT; + const u32 base = i915_gem_obj_ggtt_offset(ctx->obj); + struct sg_page_iter sg_iter; + struct i915_address_space *vm = ctx->vm; + int i = 0; + + BUG_ON(!i915_gem_obj_is_pinned(ctx->obj)); + + if (intel_ring_begin(ring, round_up(ptes * 3, 2))) { + DRM_ERROR("Could not protect context object.\n"); + return; + } + + for_each_sg_page(ctx->obj->pages->sgl, &sg_iter, ctx->obj->pages->nents, 0) { + u32 pte = vm->pte_encode(sg_page_iter_dma_address(&sg_iter), + ctx->obj->cache_level, + valid); + intel_ring_emit(ring, MI_UPDATE_GTT | (1<<22)); + /* The docs contradict themselves on the offset. They say dword + * offset, yet the low 12 bits MBZ. */ + intel_ring_emit(ring, (base & PAGE_MASK) + i); + intel_ring_emit(ring, pte); + i+=PAGE_SIZE; + } + + if (i & PAGE_SHIFT) + intel_ring_emit(ring, MI_NOOP); + + intel_ring_advance(ring); +} + +static void +enable_ctx_ptes(struct intel_ring_buffer *ring, + struct i915_hw_context *ctx) +{ + if (INTEL_INFO(ring->dev)->gen < 8) + _ctx_ptes(ring, ctx, true); +} + +static void +disable_ctx_ptes(struct intel_ring_buffer *ring, + struct i915_hw_context *ctx) +{ + if (INTEL_INFO(ring->dev)->gen < 8) + _ctx_ptes(ring, ctx, false); +} + static inline int mi_set_context(struct intel_ring_buffer *ring, struct i915_hw_context *new_context, @@ -568,6 +620,8 @@ mi_set_context(struct intel_ring_buffer *ring, if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8) flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); + enable_ctx_ptes(ring, new_context); + ret = intel_ring_begin(ring, 6); if (ret) return ret; @@ -595,6 +649,8 @@ mi_set_context(struct intel_ring_buffer *ring, intel_ring_advance(ring); + disable_ctx_ptes(ring, new_context); + return ret; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8c382a5..aa95e20 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -368,7 +368,7 @@ #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) #define MI_URB_CLEAR MI_INSTR(0x19, 0) -#define MI_UPDATE_GTT MI_INSTR(0x23, 0) +#define MI_UPDATE_GTT MI_INSTR(0x23, 1) #define MI_CLFLUSH MI_INSTR(0x27, 0) #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) #define MI_REPORT_PERF_COUNT_GGTT (1<<0)