From patchwork Fri May 9 12:09:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 4142451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A839D9F1E1 for ; Fri, 9 May 2014 12:15:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9B2DA2028D for ; Fri, 9 May 2014 12:15:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 966C8201B4 for ; Fri, 9 May 2014 12:15:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 354184A064; Fri, 9 May 2014 05:15:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id B329E4A05A for ; Fri, 9 May 2014 05:15:01 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 09 May 2014 05:15:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.97,1018,1389772800"; d="scan'208"; a="529107064" Received: from omateolo-linux2.iwi.intel.com ([172.28.253.145]) by fmsmga001.fm.intel.com with ESMTP; 09 May 2014 05:15:00 -0700 From: oscar.mateo@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 9 May 2014 13:09:02 +0100 Message-Id: <1399637360-4277-33-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1399637360-4277-1-git-send-email-oscar.mateo@intel.com> References: <1399637360-4277-1-git-send-email-oscar.mateo@intel.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 32/50] drm/i915/bdw: GEN8 new ring flush X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky The BSD invalidate bit is no longer present, and we can consolidate the blt and bsd ring flushes into one. This helps prep the code to more easily handle logical ring contexts. This partially reverts: commit 65ea32ce040a0a9a907362e9a362a842fd18cb21 Author: Ben Widawsky Date: Thu Dec 13 14:57:32 2012 -0800 drm/i915/bdw: Update MI_FLUSH_DW Signed-off-by: Ben Widawsky v2: Several rebases. Do not forget the VEBOX. v3: Due to a reorder of the patch series, make it ctx aware now. Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/intel_ringbuffer.c | 60 +++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 35e89c9..5e4e3f7 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1870,6 +1870,31 @@ static void gen6_bsd_ring_write_tail(struct intel_engine *ring, _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); } +static int gen8_ring_flush(struct intel_engine *ring, + struct i915_hw_context *ctx, + u32 invalidate, u32 flush) +{ + uint32_t cmd; + struct intel_ringbuffer *ringbuf; + + ringbuf = intel_ringbuffer_begin(ring, ctx, 4); + if (IS_ERR_OR_NULL(ringbuf)) + return (PTR_ERR(ringbuf)); + + cmd = MI_FLUSH_DW + 1; + + if (invalidate & I915_GEM_GPU_DOMAINS) + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | + MI_FLUSH_DW_OP_STOREDW; + intel_ringbuffer_emit(ringbuf, cmd); + intel_ringbuffer_emit(ringbuf, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); + intel_ringbuffer_emit(ringbuf, 0); /* upper addr */ + intel_ringbuffer_emit(ringbuf, 0); /* value */ + intel_ringbuffer_advance(ringbuf); + + return 0; +} + static int gen6_bsd_ring_flush(struct intel_engine *ring, struct i915_hw_context *ctx, u32 invalidate, u32 flush) @@ -1882,8 +1907,7 @@ static int gen6_bsd_ring_flush(struct intel_engine *ring, return ret; cmd = MI_FLUSH_DW; - if (INTEL_INFO(ring->dev)->gen >= 8) - cmd += 1; + /* * Bspec vol 1c.5 - video engine command streamer: * "If ENABLED, all TLBs will be invalidated once the flush @@ -1895,13 +1919,9 @@ static int gen6_bsd_ring_flush(struct intel_engine *ring, MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); - if (INTEL_INFO(ring->dev)->gen >= 8) { - intel_ring_emit(ring, 0); /* upper addr */ - intel_ring_emit(ring, 0); /* value */ - } else { - intel_ring_emit(ring, 0); - intel_ring_emit(ring, MI_NOOP); - } + intel_ring_emit(ring, 0); + intel_ring_emit(ring, MI_NOOP); + intel_ring_advance(ring); return 0; } @@ -1990,8 +2010,7 @@ static int gen6_ring_flush(struct intel_engine *ring, return ret; cmd = MI_FLUSH_DW; - if (INTEL_INFO(ring->dev)->gen >= 8) - cmd += 1; + /* * Bspec vol 1c.3 - blitter engine command streamer: * "If ENABLED, all TLBs will be invalidated once the flush @@ -2003,13 +2022,7 @@ static int gen6_ring_flush(struct intel_engine *ring, MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); - if (INTEL_INFO(ring->dev)->gen >= 8) { - intel_ring_emit(ring, 0); /* upper addr */ - intel_ring_emit(ring, 0); /* value */ - } else { - intel_ring_emit(ring, 0); - intel_ring_emit(ring, MI_NOOP); - } + intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); if (IS_GEN7(dev) && !invalidate && flush) @@ -2204,7 +2217,6 @@ int intel_init_bsd_ring(struct drm_device *dev) /* gen6 bsd needs a special wa for tail updates */ if (IS_GEN6(dev)) ring->submit = gen6_bsd_ring_write_tail; - ring->flush = gen6_bsd_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; @@ -2213,6 +2225,7 @@ int intel_init_bsd_ring(struct drm_device *dev) ring->submit = gen8_submit_ctx; ring->init = init_ring_common_lrc; } + ring->flush = gen8_ring_flush; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; @@ -2220,6 +2233,7 @@ int intel_init_bsd_ring(struct drm_device *dev) ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; } else { + ring->flush = gen6_bsd_ring_flush; ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; ring->irq_get = gen6_ring_get_irq; ring->irq_put = gen6_ring_put_irq; @@ -2285,7 +2299,7 @@ int intel_init_bsd2_ring(struct drm_device *dev) ring->submit = ring_write_tail; ring->init = init_ring_common; } - ring->flush = gen6_bsd_ring_flush; + ring->flush = gen8_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; @@ -2323,7 +2337,6 @@ int intel_init_blt_ring(struct drm_device *dev) ring->submit = ring_write_tail; ring->init = init_ring_common; - ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; @@ -2332,12 +2345,14 @@ int intel_init_blt_ring(struct drm_device *dev) ring->submit = gen8_submit_ctx; ring->init = init_ring_common_lrc; } + ring->flush = gen8_ring_flush; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; } else { + ring->flush = gen6_ring_flush; ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; ring->irq_get = gen6_ring_get_irq; ring->irq_put = gen6_ring_put_irq; @@ -2372,7 +2387,6 @@ int intel_init_vebox_ring(struct drm_device *dev) ring->submit = ring_write_tail; ring->init = init_ring_common; - ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; @@ -2382,12 +2396,14 @@ int intel_init_vebox_ring(struct drm_device *dev) ring->submit = gen8_submit_ctx; ring->init = init_ring_common_lrc; } + ring->flush = gen8_ring_flush; ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; } else { + ring->flush = gen6_ring_flush; ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; ring->irq_get = hsw_vebox_get_irq; ring->irq_put = hsw_vebox_put_irq;