diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 35e89c9..5e4e3f7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1870,6 +1870,31 @@ static void gen6_bsd_ring_write_tail(struct intel_engine *ring,
 		   _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
 }
 
+static int gen8_ring_flush(struct intel_engine *ring,
+			   struct i915_hw_context *ctx,
+			   u32 invalidate, u32 flush)
+{
+	uint32_t cmd;
+	struct intel_ringbuffer *ringbuf;
+
+	ringbuf = intel_ringbuffer_begin(ring, ctx, 4);
+	if (IS_ERR_OR_NULL(ringbuf))
+		return (PTR_ERR(ringbuf));
+
+	cmd = MI_FLUSH_DW + 1;
+
+	if (invalidate & I915_GEM_GPU_DOMAINS)
+		cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
+			MI_FLUSH_DW_OP_STOREDW;
+	intel_ringbuffer_emit(ringbuf, cmd);
+	intel_ringbuffer_emit(ringbuf, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
+	intel_ringbuffer_emit(ringbuf, 0); /* upper addr */
+	intel_ringbuffer_emit(ringbuf, 0); /* value */
+	intel_ringbuffer_advance(ringbuf);
+
+	return 0;
+}
+
 static int gen6_bsd_ring_flush(struct intel_engine *ring,
 			       struct i915_hw_context *ctx,
 			       u32 invalidate, u32 flush)
@@ -1882,8 +1907,7 @@ static int gen6_bsd_ring_flush(struct intel_engine *ring,
 		return ret;
 
 	cmd = MI_FLUSH_DW;
-	if (INTEL_INFO(ring->dev)->gen >= 8)
-		cmd += 1;
+
 	/*
 	 * Bspec vol 1c.5 - video engine command streamer:
 	 * "If ENABLED, all TLBs will be invalidated once the flush
@@ -1895,13 +1919,9 @@ static int gen6_bsd_ring_flush(struct intel_engine *ring,
 			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
-	if (INTEL_INFO(ring->dev)->gen >= 8) {
-		intel_ring_emit(ring, 0); /* upper addr */
-		intel_ring_emit(ring, 0); /* value */
-	} else  {
-		intel_ring_emit(ring, 0);
-		intel_ring_emit(ring, MI_NOOP);
-	}
+	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, MI_NOOP);
+
 	intel_ring_advance(ring);
 	return 0;
 }
@@ -1990,8 +2010,7 @@ static int gen6_ring_flush(struct intel_engine *ring,
 		return ret;
 
 	cmd = MI_FLUSH_DW;
-	if (INTEL_INFO(ring->dev)->gen >= 8)
-		cmd += 1;
+
 	/*
 	 * Bspec vol 1c.3 - blitter engine command streamer:
 	 * "If ENABLED, all TLBs will be invalidated once the flush
@@ -2003,13 +2022,7 @@ static int gen6_ring_flush(struct intel_engine *ring,
 			MI_FLUSH_DW_OP_STOREDW;
 	intel_ring_emit(ring, cmd);
 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
-	if (INTEL_INFO(ring->dev)->gen >= 8) {
-		intel_ring_emit(ring, 0); /* upper addr */
-		intel_ring_emit(ring, 0); /* value */
-	} else  {
-		intel_ring_emit(ring, 0);
-		intel_ring_emit(ring, MI_NOOP);
-	}
+	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 
 	if (IS_GEN7(dev) && !invalidate && flush)
@@ -2204,7 +2217,6 @@ int intel_init_bsd_ring(struct drm_device *dev)
 		/* gen6 bsd needs a special wa for tail updates */
 		if (IS_GEN6(dev))
 			ring->submit = gen6_bsd_ring_write_tail;
-		ring->flush = gen6_bsd_ring_flush;
 		ring->add_request = gen6_add_request;
 		ring->get_seqno = gen6_ring_get_seqno;
 		ring->set_seqno = ring_set_seqno;
@@ -2213,6 +2225,7 @@ int intel_init_bsd_ring(struct drm_device *dev)
 				ring->submit = gen8_submit_ctx;
 				ring->init = init_ring_common_lrc;
 			}
+			ring->flush = gen8_ring_flush;
 			ring->irq_enable_mask =
 				GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
 			ring->irq_get = gen8_ring_get_irq;
@@ -2220,6 +2233,7 @@ int intel_init_bsd_ring(struct drm_device *dev)
 			ring->dispatch_execbuffer =
 				gen8_ring_dispatch_execbuffer;
 		} else {
+			ring->flush = gen6_bsd_ring_flush;
 			ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
 			ring->irq_get = gen6_ring_get_irq;
 			ring->irq_put = gen6_ring_put_irq;
@@ -2285,7 +2299,7 @@ int intel_init_bsd2_ring(struct drm_device *dev)
 		ring->submit = ring_write_tail;
 		ring->init = init_ring_common;
 	}
-	ring->flush = gen6_bsd_ring_flush;
+	ring->flush = gen8_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
 	ring->set_seqno = ring_set_seqno;
@@ -2323,7 +2337,6 @@ int intel_init_blt_ring(struct drm_device *dev)
 
 	ring->submit = ring_write_tail;
 	ring->init = init_ring_common;
-	ring->flush = gen6_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
 	ring->set_seqno = ring_set_seqno;
@@ -2332,12 +2345,14 @@ int intel_init_blt_ring(struct drm_device *dev)
 			ring->submit = gen8_submit_ctx;
 			ring->init = init_ring_common_lrc;
 		}
+		ring->flush = gen8_ring_flush;
 		ring->irq_enable_mask =
 			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 		ring->irq_get = gen8_ring_get_irq;
 		ring->irq_put = gen8_ring_put_irq;
 		ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
 	} else {
+		ring->flush = gen6_ring_flush;
 		ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
 		ring->irq_get = gen6_ring_get_irq;
 		ring->irq_put = gen6_ring_put_irq;
@@ -2372,7 +2387,6 @@ int intel_init_vebox_ring(struct drm_device *dev)
 
 	ring->submit = ring_write_tail;
 	ring->init = init_ring_common;
-	ring->flush = gen6_ring_flush;
 	ring->add_request = gen6_add_request;
 	ring->get_seqno = gen6_ring_get_seqno;
 	ring->set_seqno = ring_set_seqno;
@@ -2382,12 +2396,14 @@ int intel_init_vebox_ring(struct drm_device *dev)
 			ring->submit = gen8_submit_ctx;
 			ring->init = init_ring_common_lrc;
 		}
+		ring->flush = gen8_ring_flush;
 		ring->irq_enable_mask =
 			GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
 		ring->irq_get = gen8_ring_get_irq;
 		ring->irq_put = gen8_ring_put_irq;
 		ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
 	} else {
+		ring->flush = gen6_ring_flush;
 		ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
 		ring->irq_get = hsw_vebox_get_irq;
 		ring->irq_put = hsw_vebox_put_irq;
