From patchwork Fri May 9 12:09:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 4142461 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0FABDBFF02 for ; Fri, 9 May 2014 12:15:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 33FD6201B4 for ; Fri, 9 May 2014 12:15:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 35751201D3 for ; Fri, 9 May 2014 12:15:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CE1C6EF82; Fri, 9 May 2014 05:15:04 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 548576EF83 for ; Fri, 9 May 2014 05:15:03 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 09 May 2014 05:15:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.97,1018,1389772800"; d="scan'208"; a="529107096" Received: from omateolo-linux2.iwi.intel.com ([172.28.253.145]) by fmsmga001.fm.intel.com with ESMTP; 09 May 2014 05:15:01 -0700 From: oscar.mateo@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 9 May 2014 13:09:03 +0100 Message-Id: <1399637360-4277-34-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1399637360-4277-1-git-send-email-oscar.mateo@intel.com> References: <1399637360-4277-1-git-send-email-oscar.mateo@intel.com> Cc: Thomas Daniel Subject: [Intel-gfx] [PATCH 33/50] drm/i915/bdw: Always write seqno to default context X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo Even though we have one Hardware Status Page per context, we are still managing the seqnos per engine. Therefore, the sequence number must be written to a consistent place for all contexts: one of the global default contexts. Signed-off-by: Thomas Daniel v2: Since get_seqno and set_seqno now look for the seqno in the engine's status page, they don't need to be changed. Signed-off-by: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 67 ++++++++++++++++++++++++++++++++- 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 33d007d..2e76ec0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -259,6 +259,7 @@ #define MI_FORCE_RESTORE (1<<1) #define MI_RESTORE_INHIBIT (1<<0) #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) +#define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2) #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) #define MI_STORE_DWORD_INDEX_SHIFT 2 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5e4e3f7..d38d824 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -781,6 +781,66 @@ gen6_add_request(struct intel_engine *ring, return 0; } +static int +gen8_nonrender_add_request_lrc(struct intel_engine *ring, + struct i915_hw_context *ctx) +{ + struct intel_ringbuffer *ringbuf; + struct i915_hw_context *dctx = ring->default_context; + struct drm_i915_gem_object *obj = dctx->engine[ring->id].obj; + u32 cmd; + + ringbuf = intel_ringbuffer_begin(ring, ctx, 6); + if (IS_ERR_OR_NULL(ringbuf)) + return (PTR_ERR(ringbuf)); + + cmd = MI_FLUSH_DW + 1; + cmd |= MI_INVALIDATE_TLB; + cmd |= MI_FLUSH_DW_OP_STOREDW; + + intel_ringbuffer_emit(ringbuf, cmd); + intel_ringbuffer_emit(ringbuf, + ((i915_gem_obj_ggtt_offset(obj)) + + (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)) | + MI_FLUSH_DW_USE_GTT); + intel_ringbuffer_emit(ringbuf, 0); /* upper addr */ + intel_ringbuffer_emit(ringbuf, ring->outstanding_lazy_seqno); + intel_ringbuffer_emit(ringbuf, MI_USER_INTERRUPT); + intel_ringbuffer_emit(ringbuf, MI_NOOP); + intel_ringbuffer_advance_and_submit(ring, ctx); + + return 0; +} + +static int +gen8_add_request_lrc(struct intel_engine *ring, + struct i915_hw_context *ctx) +{ + struct intel_ringbuffer *ringbuf; + struct i915_hw_context *dctx = ring->default_context; + struct drm_i915_gem_object *obj = dctx->engine[ring->id].obj; + u32 cmd; + + ringbuf = intel_ringbuffer_begin(ring, ctx, 6); + if (IS_ERR_OR_NULL(ringbuf)) + return (PTR_ERR(ringbuf)); + + cmd = MI_STORE_DWORD_IMM_GEN8; + cmd |= (1 << 22); /* use global GTT */ + + intel_ringbuffer_emit(ringbuf, cmd); + intel_ringbuffer_emit(ringbuf, + ((i915_gem_obj_ggtt_offset(obj)) + + (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); + intel_ringbuffer_emit(ringbuf, 0); /* upper addr */ + intel_ringbuffer_emit(ringbuf, ring->outstanding_lazy_seqno); + intel_ringbuffer_emit(ringbuf, MI_USER_INTERRUPT); + intel_ringbuffer_emit(ringbuf, MI_NOOP); + intel_ringbuffer_advance_and_submit(ring, ctx); + + return 0; +} + static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, u32 seqno) { @@ -2047,6 +2107,7 @@ int intel_init_render_ring(struct drm_device *dev) if (dev_priv->lrc_enabled) { ring->submit = gen8_submit_ctx; ring->init = init_render_ring_lrc; + ring->add_request = gen8_add_request_lrc; } ring->flush = gen8_render_ring_flush; ring->irq_get = gen8_ring_get_irq; @@ -2224,6 +2285,7 @@ int intel_init_bsd_ring(struct drm_device *dev) if (dev_priv->lrc_enabled) { ring->submit = gen8_submit_ctx; ring->init = init_ring_common_lrc; + ring->add_request = gen8_nonrender_add_request_lrc; } ring->flush = gen8_ring_flush; ring->irq_enable_mask = @@ -2294,13 +2356,14 @@ int intel_init_bsd2_ring(struct drm_device *dev) if (dev_priv->lrc_enabled) { ring->submit = gen8_submit_ctx; + ring->add_request = gen8_nonrender_add_request_lrc; ring->init = init_ring_common_lrc; } else { ring->submit = ring_write_tail; + ring->add_request = gen6_add_request; ring->init = init_ring_common; } ring->flush = gen8_ring_flush; - ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->set_seqno = ring_set_seqno; ring->irq_enable_mask = @@ -2344,6 +2407,7 @@ int intel_init_blt_ring(struct drm_device *dev) if (dev_priv->lrc_enabled) { ring->submit = gen8_submit_ctx; ring->init = init_ring_common_lrc; + ring->add_request = gen8_nonrender_add_request_lrc; } ring->flush = gen8_ring_flush; ring->irq_enable_mask = @@ -2395,6 +2459,7 @@ int intel_init_vebox_ring(struct drm_device *dev) if (dev_priv->lrc_enabled) { ring->submit = gen8_submit_ctx; ring->init = init_ring_common_lrc; + ring->add_request = gen8_nonrender_add_request_lrc; } ring->flush = gen8_ring_flush; ring->irq_enable_mask =