From patchwork Wed May 14 13:18:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 4174621 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 69C369F1C0 for ; Wed, 14 May 2014 13:21:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9E45C20340 for ; Wed, 14 May 2014 13:21:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E49F220328 for ; Wed, 14 May 2014 13:20:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A6D16E4B3; Wed, 14 May 2014 06:20:57 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 29D2F6E4B3 for ; Wed, 14 May 2014 06:20:55 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 14 May 2014 06:18:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.97,1051,1389772800"; d="scan'208"; a="432024821" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.66]) by azsmga001.ch.intel.com with ESMTP; 14 May 2014 06:17:59 -0700 Received: by rosetta (Postfix, from userid 1000) id B17E5800B6; Wed, 14 May 2014 16:18:03 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 May 2014 16:18:02 +0300 Message-Id: <1400073482-15056-1-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1400069454-6945-1-git-send-email-mika.kuoppala@intel.com> References: <1400069454-6945-1-git-send-email-mika.kuoppala@intel.com> Subject: [Intel-gfx] [PATCH] drm/i915: prevent gt fifo count underflow X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If we get the final value of zero as a count of free entries available, we will underflow our own fifo_count and then it will take a long time before we check things again. Admittedly we are in trouble already if we get into this situation, but prevent the underflow by returning early. v2: Less convoluted control flow (Daniel Vetter) Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 76dc185..bf1b661 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -154,10 +154,8 @@ static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, gen6_gt_check_fifodbg(dev_priv); } -static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) +static bool __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { - int ret = 0; - /* On VLV, FIFO will be shared by both SW and HW. * So, we need to read the FREE_ENTRIES everytime */ if (IS_VALLEYVIEW(dev_priv->dev)) @@ -173,12 +171,12 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) - ++ret; + return true; dev_priv->uncore.fifo_count = fifo; } dev_priv->uncore.fifo_count--; - return ret; + return false; } static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) @@ -642,13 +640,13 @@ gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace #define __gen6_write(x) \ static void \ gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ - u32 __fifo_ret = 0; \ + bool __fifo_failed = false; \ REG_WRITE_HEADER; \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ - __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ + __fifo_failed = __gen6_gt_wait_for_fifo(dev_priv); \ } \ __raw_i915_write##x(dev_priv, reg, val); \ - if (unlikely(__fifo_ret)) { \ + if (unlikely(__fifo_failed)) { \ gen6_gt_check_fifodbg(dev_priv); \ } \ REG_WRITE_FOOTER; \ @@ -657,14 +655,14 @@ gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace #define __hsw_write(x) \ static void \ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ - u32 __fifo_ret = 0; \ + bool __fifo_failed = false; \ REG_WRITE_HEADER; \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ - __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ + __fifo_failed = __gen6_gt_wait_for_fifo(dev_priv); \ } \ hsw_unclaimed_reg_clear(dev_priv, reg); \ __raw_i915_write##x(dev_priv, reg, val); \ - if (unlikely(__fifo_ret)) { \ + if (unlikely(__fifo_failed)) { \ gen6_gt_check_fifodbg(dev_priv); \ } \ hsw_unclaimed_reg_check(dev_priv, reg); \