diff mbox

drm/i915: Be careful with non-disp bit in PMINTRMSK

Message ID 1400237052-10371-1-git-send-email-mika.kuoppala@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala May 16, 2014, 10:44 a.m. UTC 
Bit 31 in GEN6_PMINTRMSK is not an interrupt disable bit with gen8.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Daniel Vetter May 16, 2014, 2:29 p.m. UTC | #1 
On Fri, May 16, 2014 at 01:44:12PM +0300, Mika Kuoppala wrote:
> Bit 31 in GEN6_PMINTRMSK is not an interrupt disable bit with gen8.
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Queued for -next, thanks for the patch.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 34b0766..b59e8ab 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3293,7 +3293,7 @@  static void gen8_disable_rps_interrupts(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+	I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
 	I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
 				   ~dev_priv->pm_rps_events);
 	/* Complete PM interrupt masking here doesn't race with the rps work