diff mbox

[01/11] drm/dp_helper: add defines for DP 1.2 and MST support.

Message ID 1400640904-16847-2-git-send-email-airlied@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Dave Airlie May 21, 2014, 2:54 a.m. UTC 
From: Dave Airlie <airlied@redhat.com>

This just adds the defines from the DP 1.2 spec, which we
will use later.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 include/drm/drm_dp_helper.h | 78 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

Comments

Todd Previte May 23, 2014, 4:22 a.m. UTC | #1 
> Dave Airlie <mailto:airlied@gmail.com>
> Tuesday, May 20, 2014 7:54 PM
> From: Dave Airlie <airlied@redhat.com>
>
> This just adds the defines from the DP 1.2 spec, which we
> will use later.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> ---
> include/drm/drm_dp_helper.h | 78 
> +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 78 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index cfcacec..879836d 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -37,6 +37,7 @@
> * eDP: Embedded DisplayPort version 1
> * DPI: DisplayPort Interoperability Guideline v1.1a
> * 1.2: DisplayPort 1.2
> + * MST: Multistream Transport - part of DP 1.2a
> *
> * 1.2 formally includes both eDP and DPI definitions.
> */
> @@ -103,9 +104,14 @@
> #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
>
> /* Multiple stream transport */
> +#define DP_FAUX_CAP 0x020 /* 1.2 */
> +# define DP_FAUX_CAP_1 (1 << 0)
> +
> #define DP_MSTM_CAP 0x021 /* 1.2 */
> # define DP_MST_CAP (1 << 0)
>
> +#define DP_GUID 0x030 /* 1.2 */
> +
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> # define DP_PSR_IS_SUPPORTED 1
> #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
> @@ -221,6 +227,16 @@
> # define DP_PSR_CRC_VERIFICATION (1 << 2)
> # define DP_PSR_FRAME_CAPTURE (1 << 3)
>
> +#define DP_ADAPTER_CTRL 0x1a0
> +# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
> +
> +#define DP_BRANCH_DEVICE_CTRL 0x1a1
> +# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
> +
> +#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
> +#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
> +#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> +
> #define DP_SINK_COUNT 0x200
> /* prior to 1.2 bit 7 was reserved mbz */
> # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
> @@ -230,6 +246,9 @@
> # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
> # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
> # define DP_CP_IRQ (1 << 2)
> +# define DP_MCCS_IRQ (1 << 3)
> +# define DP_DOWN_REP_MSG_RDY (1 << 4) /* DP MST */
> +# define DP_UP_REQ_MSG_RDY (1 << 5) /* DP MST */
> # define DP_SINK_SPECIFIC_IRQ (1 << 6)
>
> #define DP_LANE0_1_STATUS 0x202
> @@ -294,6 +313,13 @@
> #define DP_TEST_SINK 0x270
> #define DP_TEST_SINK_START (1 << 0)
>
> +#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
> +# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
> +# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
> +
> +#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
> +/* up to ID_SLOT_63 at 0x2ff */
> +
> #define DP_SOURCE_OUI 0x300
> #define DP_SINK_OUI 0x400
> #define DP_BRANCH_OUI 0x500
> @@ -303,6 +329,21 @@
> # define DP_SET_POWER_D3 0x2
> # define DP_SET_POWER_MASK 0x3
>
> +#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
> +#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
> +#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
> +#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
> +
> +#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
> +/* 0-5 sink count */
> +# define DP_SINK_COUNT_CP_READY (1 << 6)
> +
> +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
> +
> +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
> +
> +#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
> +
> #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
> # define DP_PSR_LINK_CRC_ERROR (1 << 0)
> # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
> @@ -319,6 +360,43 @@
> # define DP_PSR_SINK_INTERNAL_ERROR 7
> # define DP_PSR_SINK_STATE_MASK 0x07
>
> +/* DP 1.2 Sideband message defines */
> +/* peer device type - DP 1.2a Table 2-92 */
> +#define DP_PEER_DEVICE_NONE 0x0
> +#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
> +#define DP_PEER_DEVICE_MST_BRANCHING 0x2
> +#define DP_PEER_DEVICE_SST_SINK 0x3
> +#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
> +
> +/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
> +#define DP_LINK_ADDRESS 0x01
> +#define DP_CONNECTION_STATUS_NOTIFY 0x02
> +#define DP_ENUM_PATH_RESOURCES 0x10
> +#define DP_ALLOCATE_PAYLOAD 0x11
> +#define DP_QUERY_PAYLOAD 0x12
> +#define DP_RESOURCE_STATUS_NOTIFY 0x13
> +#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
> +#define DP_REMOTE_DPCD_READ 0x20
> +#define DP_REMOTE_DPCD_WRITE 0x21
> +#define DP_REMOTE_I2C_READ 0x22
> +#define DP_REMOTE_I2C_WRITE 0x23
> +#define DP_POWER_UP_PHY 0x24
> +#define DP_POWER_DOWN_PHY 0x25
> +#define DP_SINK_EVENT_NOTIFY 0x30
> +#define DP_QUERY_STREAM_ENC_STATUS 0x38
> +
> +/* DP 1.2 MST sideband nak reasons - table 2.84 */
> +#define DP_NAK_WRITE_FAILURE 0x01
> +#define DP_NAK_INVALID_READ 0x02
> +#define DP_NAK_CRC_FAILURE 0x03
> +#define DP_NAK_BAD_PARAM 0x04
> +#define DP_NAK_DEFER 0x05
> +#define DP_NAK_LINK_FAILURE 0x06
> +#define DP_NAK_NO_RESOURCES 0x07
> +#define DP_NAK_DPCD_FAIL 0x08
> +#define DP_NAK_I2C_NAK 0x09
> +#define DP_NAK_ALLOCATE_FAIL 0x0a
> +
> #define MODE_I2C_START 1
> #define MODE_I2C_WRITE 2
> #define MODE_I2C_READ 4
Constant definitions look good.

Reviewed-by: Todd Previte <tprevite@gmail.com>

> Dave Airlie <mailto:airlied@gmail.com>
> Tuesday, May 20, 2014 7:54 PM
> Hey,
>
> So this set is pretty close to what I think we should be merging 
> initially,
>
> Since the last set, it makes fbcon and suspend/resume work a lot better,
>
> I've also fixed a couple of bugs in -intel that make things work a lot
> better.
>
> I've bashed on this a bit using kms-flip from intel-gpu-tools, hacked
> to add 3 monitor support.
>
> It still generates a fair few i915 state checker backtraces, and some
> of them are fairly hard to work out, it might be we should just tone
> down the state checker for encoders/connectors with no actual hw backing
> them.
>
> Dave.
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jingoo Han May 23, 2014, 5:57 a.m. UTC | #2 
On Wednesday, May 21, 2014 11:55 AM, Dave Airlie wrote:
> 
> From: Dave Airlie <airlied@redhat.com>
> 
> This just adds the defines from the DP 1.2 spec, which we
> will use later.
> 
> Signed-off-by: Dave Airlie <airlied@redhat.com>

I checked this patch by using DP 1.2 spec. These definitions
are correct. Thank you.

Reviewed-by: Jingoo Han <jg1.han@samsung.com>

Best regards,
Jingoo Han

> ---
>  include/drm/drm_dp_helper.h | 78 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index cfcacec..879836d 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -37,6 +37,7 @@
>   * eDP: Embedded DisplayPort version 1
>   * DPI: DisplayPort Interoperability Guideline v1.1a
>   * 1.2: DisplayPort 1.2
> + * MST: Multistream Transport - part of DP 1.2a
>   *
>   * 1.2 formally includes both eDP and DPI definitions.
>   */
> @@ -103,9 +104,14 @@
>  #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
> 
>  /* Multiple stream transport */
> +#define DP_FAUX_CAP			    0x020   /* 1.2 */
> +# define DP_FAUX_CAP_1			    (1 << 0)
> +
>  #define DP_MSTM_CAP			    0x021   /* 1.2 */
>  # define DP_MST_CAP			    (1 << 0)
> 
> +#define DP_GUID				    0x030   /* 1.2 */
> +
>  #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
>  # define DP_PSR_IS_SUPPORTED                1
>  #define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
> @@ -221,6 +227,16 @@
>  # define DP_PSR_CRC_VERIFICATION	    (1 << 2)
>  # define DP_PSR_FRAME_CAPTURE		    (1 << 3)
> 
> +#define DP_ADAPTER_CTRL			    0x1a0
> +# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
> +
> +#define DP_BRANCH_DEVICE_CTRL		    0x1a1
> +# define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
> +
> +#define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
> +#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
> +#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> +
>  #define DP_SINK_COUNT			    0x200
>  /* prior to 1.2 bit 7 was reserved mbz */
>  # define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))
> @@ -230,6 +246,9 @@
>  # define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
>  # define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
>  # define DP_CP_IRQ			    (1 << 2)
> +# define DP_MCCS_IRQ			    (1 << 3)
> +# define DP_DOWN_REP_MSG_RDY		    (1 << 4) /* DP MST */
> +# define DP_UP_REQ_MSG_RDY		    (1 << 5) /* DP MST */
>  # define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
> 
>  #define DP_LANE0_1_STATUS		    0x202
> @@ -294,6 +313,13 @@
>  #define DP_TEST_SINK			    0x270
>  #define DP_TEST_SINK_START	    (1 << 0)
> 
> +#define DP_PAYLOAD_TABLE_UPDATE_STATUS      0x2c0   /* 1.2 MST */
> +# define DP_PAYLOAD_TABLE_UPDATED           (1 << 0)
> +# define DP_PAYLOAD_ACT_HANDLED             (1 << 1)
> +
> +#define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */
> +/* up to ID_SLOT_63 at 0x2ff */
> +
>  #define DP_SOURCE_OUI			    0x300
>  #define DP_SINK_OUI			    0x400
>  #define DP_BRANCH_OUI			    0x500
> @@ -303,6 +329,21 @@
>  # define DP_SET_POWER_D3                    0x2
>  # define DP_SET_POWER_MASK                  0x3
> 
> +#define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */
> +#define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */
> +#define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */
> +#define DP_SIDEBAND_MSG_UP_REQ_BASE	    0x1600   /* 1.2 MST */
> +
> +#define DP_SINK_COUNT_ESI		    0x2002   /* 1.2 */
> +/* 0-5 sink count */
> +# define DP_SINK_COUNT_CP_READY             (1 << 6)
> +
> +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
> +
> +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
> +
> +#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
> +
>  #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
>  # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
>  # define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
> @@ -319,6 +360,43 @@
>  # define DP_PSR_SINK_INTERNAL_ERROR         7
>  # define DP_PSR_SINK_STATE_MASK             0x07
> 
> +/* DP 1.2 Sideband message defines */
> +/* peer device type - DP 1.2a Table 2-92 */
> +#define DP_PEER_DEVICE_NONE		0x0
> +#define DP_PEER_DEVICE_SOURCE_OR_SST	0x1
> +#define DP_PEER_DEVICE_MST_BRANCHING	0x2
> +#define DP_PEER_DEVICE_SST_SINK		0x3
> +#define DP_PEER_DEVICE_DP_LEGACY_CONV	0x4
> +
> +/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
> +#define DP_LINK_ADDRESS			0x01
> +#define DP_CONNECTION_STATUS_NOTIFY	0x02
> +#define DP_ENUM_PATH_RESOURCES		0x10
> +#define DP_ALLOCATE_PAYLOAD		0x11
> +#define DP_QUERY_PAYLOAD		0x12
> +#define DP_RESOURCE_STATUS_NOTIFY	0x13
> +#define DP_CLEAR_PAYLOAD_ID_TABLE	0x14
> +#define DP_REMOTE_DPCD_READ		0x20
> +#define DP_REMOTE_DPCD_WRITE		0x21
> +#define DP_REMOTE_I2C_READ		0x22
> +#define DP_REMOTE_I2C_WRITE		0x23
> +#define DP_POWER_UP_PHY			0x24
> +#define DP_POWER_DOWN_PHY		0x25
> +#define DP_SINK_EVENT_NOTIFY		0x30
> +#define DP_QUERY_STREAM_ENC_STATUS	0x38
> +
> +/* DP 1.2 MST sideband nak reasons - table 2.84 */
> +#define DP_NAK_WRITE_FAILURE		0x01
> +#define DP_NAK_INVALID_READ		0x02
> +#define DP_NAK_CRC_FAILURE		0x03
> +#define DP_NAK_BAD_PARAM		0x04
> +#define DP_NAK_DEFER			0x05
> +#define DP_NAK_LINK_FAILURE		0x06
> +#define DP_NAK_NO_RESOURCES		0x07
> +#define DP_NAK_DPCD_FAIL		0x08
> +#define DP_NAK_I2C_NAK			0x09
> +#define DP_NAK_ALLOCATE_FAIL		0x0a
> +
>  #define MODE_I2C_START	1
>  #define MODE_I2C_WRITE	2
>  #define MODE_I2C_READ	4
> --
> 1.9.0
diff mbox

Patch

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index cfcacec..879836d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -37,6 +37,7 @@ 
  * eDP: Embedded DisplayPort version 1
  * DPI: DisplayPort Interoperability Guideline v1.1a
  * 1.2: DisplayPort 1.2
+ * MST: Multistream Transport - part of DP 1.2a
  *
  * 1.2 formally includes both eDP and DPI definitions.
  */
@@ -103,9 +104,14 @@ 
 #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
 
 /* Multiple stream transport */
+#define DP_FAUX_CAP			    0x020   /* 1.2 */
+# define DP_FAUX_CAP_1			    (1 << 0)
+
 #define DP_MSTM_CAP			    0x021   /* 1.2 */
 # define DP_MST_CAP			    (1 << 0)
 
+#define DP_GUID				    0x030   /* 1.2 */
+
 #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
 # define DP_PSR_IS_SUPPORTED                1
 #define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
@@ -221,6 +227,16 @@ 
 # define DP_PSR_CRC_VERIFICATION	    (1 << 2)
 # define DP_PSR_FRAME_CAPTURE		    (1 << 3)
 
+#define DP_ADAPTER_CTRL			    0x1a0
+# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
+
+#define DP_BRANCH_DEVICE_CTRL		    0x1a1
+# define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
+
+#define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
+#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
+#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
+
 #define DP_SINK_COUNT			    0x200
 /* prior to 1.2 bit 7 was reserved mbz */
 # define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))
@@ -230,6 +246,9 @@ 
 # define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
 # define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
 # define DP_CP_IRQ			    (1 << 2)
+# define DP_MCCS_IRQ			    (1 << 3)
+# define DP_DOWN_REP_MSG_RDY		    (1 << 4) /* DP MST */
+# define DP_UP_REQ_MSG_RDY		    (1 << 5) /* DP MST */
 # define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
 
 #define DP_LANE0_1_STATUS		    0x202
@@ -294,6 +313,13 @@ 
 #define DP_TEST_SINK			    0x270
 #define DP_TEST_SINK_START	    (1 << 0)
 
+#define DP_PAYLOAD_TABLE_UPDATE_STATUS      0x2c0   /* 1.2 MST */
+# define DP_PAYLOAD_TABLE_UPDATED           (1 << 0)
+# define DP_PAYLOAD_ACT_HANDLED             (1 << 1)
+
+#define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */
+/* up to ID_SLOT_63 at 0x2ff */
+
 #define DP_SOURCE_OUI			    0x300
 #define DP_SINK_OUI			    0x400
 #define DP_BRANCH_OUI			    0x500
@@ -303,6 +329,21 @@ 
 # define DP_SET_POWER_D3                    0x2
 # define DP_SET_POWER_MASK                  0x3
 
+#define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */
+#define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */
+#define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */
+#define DP_SIDEBAND_MSG_UP_REQ_BASE	    0x1600   /* 1.2 MST */
+
+#define DP_SINK_COUNT_ESI		    0x2002   /* 1.2 */
+/* 0-5 sink count */
+# define DP_SINK_COUNT_CP_READY             (1 << 6)
+
+#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
+
+#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
+
+#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
+
 #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
 # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
 # define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
@@ -319,6 +360,43 @@ 
 # define DP_PSR_SINK_INTERNAL_ERROR         7
 # define DP_PSR_SINK_STATE_MASK             0x07
 
+/* DP 1.2 Sideband message defines */
+/* peer device type - DP 1.2a Table 2-92 */
+#define DP_PEER_DEVICE_NONE		0x0
+#define DP_PEER_DEVICE_SOURCE_OR_SST	0x1
+#define DP_PEER_DEVICE_MST_BRANCHING	0x2
+#define DP_PEER_DEVICE_SST_SINK		0x3
+#define DP_PEER_DEVICE_DP_LEGACY_CONV	0x4
+
+/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
+#define DP_LINK_ADDRESS			0x01
+#define DP_CONNECTION_STATUS_NOTIFY	0x02
+#define DP_ENUM_PATH_RESOURCES		0x10
+#define DP_ALLOCATE_PAYLOAD		0x11
+#define DP_QUERY_PAYLOAD		0x12
+#define DP_RESOURCE_STATUS_NOTIFY	0x13
+#define DP_CLEAR_PAYLOAD_ID_TABLE	0x14
+#define DP_REMOTE_DPCD_READ		0x20
+#define DP_REMOTE_DPCD_WRITE		0x21
+#define DP_REMOTE_I2C_READ		0x22
+#define DP_REMOTE_I2C_WRITE		0x23
+#define DP_POWER_UP_PHY			0x24
+#define DP_POWER_DOWN_PHY		0x25
+#define DP_SINK_EVENT_NOTIFY		0x30
+#define DP_QUERY_STREAM_ENC_STATUS	0x38
+
+/* DP 1.2 MST sideband nak reasons - table 2.84 */
+#define DP_NAK_WRITE_FAILURE		0x01
+#define DP_NAK_INVALID_READ		0x02
+#define DP_NAK_CRC_FAILURE		0x03
+#define DP_NAK_BAD_PARAM		0x04
+#define DP_NAK_DEFER			0x05
+#define DP_NAK_LINK_FAILURE		0x06
+#define DP_NAK_NO_RESOURCES		0x07
+#define DP_NAK_DPCD_FAIL		0x08
+#define DP_NAK_I2C_NAK			0x09
+#define DP_NAK_ALLOCATE_FAIL		0x0a
+
 #define MODE_I2C_START	1
 #define MODE_I2C_WRITE	2
 #define MODE_I2C_READ	4