diff mbox

[v2,4/5] drm/i915: Wait for pending page flips before enabling/disabling the primary plane

Message ID 1400670286-32102-1-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä May 21, 2014, 11:04 a.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have to write to the primary plane base address registrer when we
enable/disable the primary plane in response to sprite coverage. Those
writes will cause the flip counter to increment which could interfere
with the detection of CS flip completion. We could end up completing
CS flips before the CS has even executed the commands from the ring.

To avoid such issues, wait for CS flips to finish before we toggle the
primary plane on/off.

v2: Rebased due to atomic sprite update changes

Testcase: igt/kms_mmio_vs_cs_flip/setplane_vs_cs_flip
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_drv.h     | 2 ++
 drivers/gpu/drm/i915/intel_sprite.c  | 3 +++
 3 files changed, 6 insertions(+), 1 deletion(-)

Comments

Rodrigo Vivi May 21, 2014, 10:29 p.m. UTC | #1
Reviewed-by Rodrigo Vivi <rodrigo.vivi@gmail.com>


On Wed, May 21, 2014 at 4:04 AM, <ville.syrjala@linux.intel.com> wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have to write to the primary plane base address registrer when we
> enable/disable the primary plane in response to sprite coverage. Those
> writes will cause the flip counter to increment which could interfere
> with the detection of CS flip completion. We could end up completing
> CS flips before the CS has even executed the commands from the ring.
>
> To avoid such issues, wait for CS flips to finish before we toggle the
> primary plane on/off.
>
> v2: Rebased due to atomic sprite update changes
>
> Testcase: igt/kms_mmio_vs_cs_flip/setplane_vs_cs_flip
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_drv.h     | 2 ++
>  drivers/gpu/drm/i915/intel_sprite.c  | 3 +++
>  3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8ca8b2f..849bc71 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3291,7 +3291,7 @@ bool intel_has_pending_fb_unpin(struct drm_device
> *dev)
>         return false;
>  }
>
> -static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
> +void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
>  {
>         struct drm_device *dev = crtc->dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index a78eb75..b9b13eb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -801,6 +801,8 @@ int valleyview_get_vco(struct drm_i915_private
> *dev_priv);
>  void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>                                  struct intel_crtc_config *pipe_config);
>  int intel_format_to_fourcc(int format);
> +void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
> +
>
>  /* intel_dp.c */
>  void intel_dp_init(struct drm_device *dev, int output_reg, enum port
> port);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 7780f6c..d6acd6b 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1018,6 +1018,9 @@ intel_update_plane(struct drm_plane *plane, struct
> drm_crtc *crtc,
>
>                 intel_crtc->primary_enabled = primary_enabled;
>
> +               if (primary_was_enabled != primary_enabled)
> +                       intel_crtc_wait_for_pending_flips(crtc);
> +
>                 if (primary_was_enabled && !primary_enabled)
>                         intel_pre_disable_primary(crtc);
>
> --
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8ca8b2f..849bc71 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3291,7 +3291,7 @@  bool intel_has_pending_fb_unpin(struct drm_device *dev)
 	return false;
 }
 
-static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
+void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a78eb75..b9b13eb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -801,6 +801,8 @@  int valleyview_get_vco(struct drm_i915_private *dev_priv);
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_config *pipe_config);
 int intel_format_to_fourcc(int format);
+void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
+
 
 /* intel_dp.c */
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 7780f6c..d6acd6b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1018,6 +1018,9 @@  intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 		intel_crtc->primary_enabled = primary_enabled;
 
+		if (primary_was_enabled != primary_enabled)
+			intel_crtc_wait_for_pending_flips(crtc);
+
 		if (primary_was_enabled && !primary_enabled)
 			intel_pre_disable_primary(crtc);