| Message ID | 1401318418-11860-1-git-send-email-benjamin.widawsky@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, May 28, 2014 at 04:06:58PM -0700, Ben Widawsky wrote: > The PDPs seem to get screwed up otherwise, specifically PDP0. I am not > really clear why this is required, it just works with full PPGTT. > > v2: Only do it for gen8, to limit regression potential > > v3: Fix the bugzilla links I should note there is a problem with this patch. Without full PPGTT, we also do a restore inhibit on the default context, and therefore any test which is running and not using contexts (like everything in IGT) is programming restore inhibit as well as force restore, which as has been pointed out in the semaphore series is weird at best. All I know is the patch fixed at least a few of the bugs mentioned below. I guess we'll figure out what to do when the QA results come in. [snip]
On Wed, May 28, 2014 at 10:54:21PM -0700, Ben Widawsky wrote: > On Wed, May 28, 2014 at 04:06:58PM -0700, Ben Widawsky wrote: > > The PDPs seem to get screwed up otherwise, specifically PDP0. I am not > > really clear why this is required, it just works with full PPGTT. > > > > v2: Only do it for gen8, to limit regression potential > > > > v3: Fix the bugzilla links > > I should note there is a problem with this patch. Without full PPGTT, we > also do a restore inhibit on the default context, and therefore any test > which is running and not using contexts (like everything in IGT) is > programming restore inhibit as well as force restore, which as has been > pointed out in the semaphore series is weird at best. > > All I know is the patch fixed at least a few of the bugs mentioned > below. I guess we'll figure out what to do when the QA results come in. > > [snip] > Okay, now I am really confused. I've changed machines and none of these tests are passing for me now. Until I figured out what happened, please ignore this thread. Sorry for the noise.
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 3ffe308..c5330ab 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -568,6 +568,9 @@ mi_set_context(struct intel_engine_cs *ring, else intel_ring_emit(ring, MI_NOOP); + if (INTEL_INFO(ring->dev)->gen == 8) + hw_flags |= MI_FORCE_RESTORE; + intel_ring_emit(ring, MI_NOOP); intel_ring_emit(ring, MI_SET_CONTEXT); intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
The PDPs seem to get screwed up otherwise, specifically PDP0. I am not really clear why this is required, it just works with full PPGTT. v2: Only do it for gen8, to limit regression potential v3: Fix the bugzilla links Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938 Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ 1 file changed, 3 insertions(+)