resume timings

Commit Message

Jesse Barnes June 5, 2014, 3:48 p.m. UTC

---
 drivers/gpu/drm/i915/i915_drv.c      | 6 ++++++
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 2 files changed, 15 insertions(+)

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0f9e836..a2036b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -625,6 +625,8 @@  static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	DRM_ERROR("start thaw\n");
+
 	if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 	    restore_gtt_mappings) {
 		mutex_lock(&dev->struct_mutex);
@@ -652,7 +654,9 @@  static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 
 		intel_modeset_init_hw(dev);
 
+		DRM_ERROR("hw state start\n");
 		schedule_work(&dev_priv->hw_restore_work);
+		DRM_ERROR("hw state end\n");
 
 		/*
 		 * ... but also need to make sure that hotplug processing
@@ -685,6 +689,8 @@  static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 	mutex_unlock(&dev_priv->modeset_restore_lock);
 
 	intel_runtime_pm_put(dev_priv);
+
+	DRM_ERROR("end thaw\n");
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6d6b0f2..472b7f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12175,7 +12175,9 @@  void intel_modeset_setup_hw_state(struct drm_device *dev,
 	struct intel_encoder *encoder;
 	int i;
 
+	DRM_ERROR("\n");
 	intel_modeset_readout_hw_state(dev);
+	DRM_ERROR("readout complete\n");
 
 	/*
 	 * Now that we have the config, copy it to each CRTC struct
@@ -12197,12 +12199,16 @@  void intel_modeset_setup_hw_state(struct drm_device *dev,
 		intel_sanitize_encoder(encoder);
 	}
 
+	DRM_ERROR("done with encoder sanitize\n");
+
 	for_each_pipe(pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 		intel_sanitize_crtc(crtc);
 		intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
 	}
 
+	DRM_ERROR("done with crtc sanitize\n");
+
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 
@@ -12215,6 +12221,8 @@  void intel_modeset_setup_hw_state(struct drm_device *dev,
 		pll->on = false;
 	}
 
+	DRM_ERROR("done with pll enable\n");
+
 	if (HAS_PCH_SPLIT(dev))
 		ilk_wm_get_hw_state(dev);
 
@@ -12231,6 +12239,7 @@  void intel_modeset_setup_hw_state(struct drm_device *dev,
 
 			__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
 					 crtc->primary->fb);
+			DRM_ERROR("done with modeset on %d\n", pipe);
 		}
 	} else {
 		intel_modeset_update_staged_output_state(dev);