From patchwork Tue Jun 10 14:30:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Wood X-Patchwork-Id: 4329221 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 402F69F3B4 for ; Tue, 10 Jun 2014 14:31:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0CD49202AE for ; Tue, 10 Jun 2014 14:31:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8BB7C202C8 for ; Tue, 10 Jun 2014 14:31:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E82ED6E026; Tue, 10 Jun 2014 07:31:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f178.google.com (mail-wi0-f178.google.com [209.85.212.178]) by gabe.freedesktop.org (Postfix) with ESMTP id 3CCC96E026 for ; Tue, 10 Jun 2014 07:31:02 -0700 (PDT) Received: by mail-wi0-f178.google.com with SMTP id n15so3227437wiw.17 for ; Tue, 10 Jun 2014 07:31:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=H3Tp52/9aDhkLbTVD84mU53CBJ7TAxWAkZrg7cBpi8Y=; b=FPd31WnRnMvqE/7E/pkTtLR6b/9XatrvpaXQYmEzOV+ful6gdydZN5WrNGW0hyAmtd YYl17A4I6YQZY/gNfVyMiOwMv91ZmXUA0B5N5SMQDK+71x3TfMrO0guYfMYLgK1sojZh LQMEyzonCEURn7otwsfZZ+3eFLjulyF5fwUeKiHz3Ydg5nRlAcDlbWHKfXZLGQOWTfqf ydMoiVWZntoR2h8gaxwfvx1vo0/+JBEHyGrCK3o61712A7xTUS8lse3+QUNpNpl3qinv ZCXjPE2wZyCNBxcBuduSMQjItMCyNP/GBlqidx+ZonOEnK1qFinqA4gAh/+khaMrlvnN +GJQ== X-Gm-Message-State: ALoCoQn0UfkZMq4bXJIBvp2zg5p3jf2etcX+QtNnKPMPikTNTVcnA/Zxn4e5oBQhbpD8XBWx/ePI X-Received: by 10.180.14.132 with SMTP id p4mr20686625wic.55.1402410661110; Tue, 10 Jun 2014 07:31:01 -0700 (PDT) Received: from pistachio.icx.intel.com ([83.217.123.106]) by mx.google.com with ESMTPSA id ci16sm379523wjb.5.2014.06.10.07.30.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Jun 2014 07:31:00 -0700 (PDT) From: Thomas Wood To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Jun 2014 15:30:52 +0100 Message-Id: <1402410657-4768-2-git-send-email-thomas.wood@intel.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1402410657-4768-1-git-send-email-thomas.wood@intel.com> References: <1402410657-4768-1-git-send-email-thomas.wood@intel.com> Subject: [Intel-gfx] [i-g-t 2/7] lib: remove /** from comments that are not API documentation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP These comments are not gtk-doc comments, so replacing /** with /* prevents any gtk-doc warnings. Signed-off-by: Thomas Wood --- lib/i915_3d.h | 26 ++-- lib/intel_reg.h | 404 +++++++++++++++++++++++++------------------------- lib/rendercopy_gen8.c | 6 +- 3 files changed, 218 insertions(+), 218 deletions(-) diff --git a/lib/i915_3d.h b/lib/i915_3d.h index 04531f3..eea379c 100644 --- a/lib/i915_3d.h +++ b/lib/i915_3d.h @@ -324,7 +324,7 @@ enum i915_fs_channel { (z##_CHANNEL_VAL << Z_CHANNEL_SHIFT) | \ (w##_CHANNEL_VAL << W_CHANNEL_SHIFT) -/** +/* * Construct an operand description for using a register with no swizzling */ #define i915_fs_operand_reg(reg) \ @@ -333,17 +333,17 @@ enum i915_fs_channel { #define i915_fs_operand_reg_negate(reg) \ i915_fs_operand(reg, NEG_X, NEG_Y, NEG_Z, NEG_W) -/** +/* * Returns an operand containing (0.0, 0.0, 0.0, 0.0). */ #define i915_fs_operand_zero() i915_fs_operand(FS_R0, ZERO, ZERO, ZERO, ZERO) -/** +/* * Returns an unused operand */ #define i915_fs_operand_none() i915_fs_operand_zero() -/** +/* * Returns an operand containing (1.0, 1.0, 1.0, 1.0). */ #define i915_fs_operand_one() i915_fs_operand(FS_R0, ONE, ONE, ONE, ONE) @@ -351,7 +351,7 @@ enum i915_fs_channel { #define i915_get_hardware_channel_val(val, shift, negate) \ (((val & 0x7) << shift) | ((val & 0x8) ? negate : 0)) -/** +/* * Outputs a fragment shader command to declare a sampler or texture register. */ #define i915_fs_dcl(reg) \ @@ -519,19 +519,19 @@ enum i915_fs_channel { i915_fs_operand_none(), \ i915_fs_operand_none()) -/** Add operand0 and operand1 and put the result in dest_reg */ +/* Add operand0 and operand1 and put the result in dest_reg */ #define i915_fs_add(dest_reg, operand0, operand1) \ i915_fs_arith (ADD, dest_reg, \ operand0, operand1, \ i915_fs_operand_none()) -/** Multiply operand0 and operand1 and put the result in dest_reg */ +/* Multiply operand0 and operand1 and put the result in dest_reg */ #define i915_fs_mul(dest_reg, operand0, operand1) \ i915_fs_arith (MUL, dest_reg, \ operand0, operand1, \ i915_fs_operand_none()) -/** Computes 1/sqrt(operand0.replicate_swizzle) puts the result in dest_reg */ +/* Computes 1/sqrt(operand0.replicate_swizzle) puts the result in dest_reg */ #define i915_fs_rsq(dest_reg, dest_mask, operand0) \ do { \ if (dest_mask) { \ @@ -547,13 +547,13 @@ enum i915_fs_channel { } \ } while (0) -/** Puts the minimum of operand0 and operand1 in dest_reg */ +/* Puts the minimum of operand0 and operand1 in dest_reg */ #define i915_fs_min(dest_reg, operand0, operand1) \ i915_fs_arith (MIN, dest_reg, \ operand0, operand1, \ i915_fs_operand_none()) -/** Puts the maximum of operand0 and operand1 in dest_reg */ +/* Puts the maximum of operand0 and operand1 in dest_reg */ #define i915_fs_max(dest_reg, operand0, operand1) \ i915_fs_arith (MAX, dest_reg, \ operand0, operand1, \ @@ -562,7 +562,7 @@ enum i915_fs_channel { #define i915_fs_cmp(dest_reg, operand0, operand1, operand2) \ i915_fs_arith (CMP, dest_reg, operand0, operand1, operand2) -/** Perform operand0 * operand1 + operand2 and put the result in dest_reg */ +/* Perform operand0 * operand1 + operand2 and put the result in dest_reg */ #define i915_fs_mad(dest_reg, dest_mask, op0, op1, op2) \ do { \ if (dest_mask) { \ @@ -581,7 +581,7 @@ enum i915_fs_channel { } \ } while (0) -/** +/* * Perform a 3-component dot-product of operand0 and operand1 and put the * resulting scalar in the channels of dest_reg specified by the dest_mask. */ @@ -597,7 +597,7 @@ enum i915_fs_channel { } \ } while (0) -/** +/* * Sets up local state for accumulating a fragment shader buffer. * * \param x maximum number of shader commands that may be used between diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 84e05e4..f8ad71f 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -26,7 +26,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ -/** @file +/* @file * Register names and fields for Intel graphics. */ @@ -322,19 +322,19 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VCLK_DIVISOR_VGA0 0x6000 #define VCLK_DIVISOR_VGA1 0x6004 #define VCLK_POST_DIV 0x6010 -/** Selects a post divisor of 4 instead of 2. */ +/* Selects a post divisor of 4 instead of 2. */ # define VGA1_PD_P2_DIV_4 (1 << 15) -/** Overrides the p2 post divisor field */ +/* Overrides the p2 post divisor field */ # define VGA1_PD_P1_DIV_2 (1 << 13) # define VGA1_PD_P1_SHIFT 8 -/** P1 value is 2 greater than this field */ +/* P1 value is 2 greater than this field */ # define VGA1_PD_P1_MASK (0x1f << 8) -/** Selects a post divisor of 4 instead of 2. */ +/* Selects a post divisor of 4 instead of 2. */ # define VGA0_PD_P2_DIV_4 (1 << 7) -/** Overrides the p2 post divisor field */ +/* Overrides the p2 post divisor field */ # define VGA0_PD_P1_DIV_2 (1 << 5) # define VGA0_PD_P1_SHIFT 0 -/** P1 value is 2 greater than this field */ +/* P1 value is 2 greater than this field */ # define VGA0_PD_P1_MASK (0x1f << 0) #define POST_DIV_SELECT 0x70 @@ -571,7 +571,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PGETBL_ADDR_MASK 0xFFFFF000 #define PGETBL_ENABLE_MASK 0x00000001 #define PGETBL_ENABLED 0x00000001 -/** Added in 965G, this field has the actual size of the global GTT */ +/* Added in 965G, this field has the actual size of the global GTT */ #define PGETBL_SIZE_MASK 0x0000000e #define PGETBL_SIZE_512KB (0 << 1) #define PGETBL_SIZE_256KB (1 << 1) @@ -592,10 +592,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PTE_MAPPING_TYPE_MASK (3 << 1) #define PTE_VALID (1 << 0) -/** @defgroup PGE_ERR +/* @defgroup PGE_ERR * @{ */ -/** Page table debug register for i845 */ +/* Page table debug register for i845 */ #define PGE_ERR 0x2024 #define PGE_ERR_ADDR_MASK 0xFFFFF000 #define PGE_ERR_ID_MASK 0x00000038 @@ -615,12 +615,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PGE_ERR_ILLEGAL_TRX 0x00000004 #define PGE_ERR_LOCAL_MEM 0x00000005 #define PGE_ERR_TILED 0x00000006 -/** @} */ +/* @} */ -/** @defgroup PGTBL_ER +/* @defgroup PGTBL_ER * @{ */ -/** Page table debug register for i945 */ +/* Page table debug register for i945 */ # define PGTBL_ER 0x2024 # define PGTBL_ERR_MT_TILING (1 << 27) # define PGTBL_ERR_MT_GTT_PTE (1 << 26) @@ -641,7 +641,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define PGTBL_ERR_DISPA_GTT_PTE (1 << 4) # define PGTBL_ERR_HOST_PTE_DATA (1 << 1) # define PGTBL_ERR_HOST_GTT_PTE (1 << 0) -/** @} */ +/* @} */ /* Ring buffer registers, p277, overview p19 */ @@ -880,7 +880,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PP_STATUS 0x61200 # define PP_ON (1 << 31) -/** +/* * Indicates that all dependencies of the panel are on: * * - PLL enabled @@ -954,12 +954,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ # define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ -/** +/* * The i830 generation, in DAC/serial mode, defines p1 as two plus this * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. */ # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 -/** +/* * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). */ @@ -991,7 +991,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff -/** +/* * SDVO multiplier for 945G/GM. Not used on 965. * * \sa DPLL_MD_UDI_MULTIPLIER_MASK @@ -1000,24 +1000,24 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define SDVO_MULTIPLIER_SHIFT_HIRES 4 # define SDVO_MULTIPLIER_SHIFT_VGA 0 -/** @defgroup DPLL_MD +/* @defgroup DPLL_MD * @{ */ -/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ +/* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ #define DPLL_A_MD 0x0601c -/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ +/* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ #define DPLL_B_MD 0x06020 -/** +/* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * * Value is pixels minus 1. Must be set to 1 pixel for SDVO. */ # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 -/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ +/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 -/** +/* * SDVO/UDI pixel multiplier. * * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus @@ -1036,13 +1036,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 -/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. +/* SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... */ # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 -/** @} */ +/* @} */ #define DPLL_TEST 0x606c # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) @@ -1086,7 +1086,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) -/** +/* * This bit must be set on the 830 to prevent hangs when turning off the * overlay scaler. */ @@ -1106,12 +1106,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) # define MAG_CLOCK_GATE_DISABLE (1 << 5) -/** This bit must be unset on 855,865 */ +/* This bit must be unset on 855,865 */ # define MECI_CLOCK_GATE_DISABLE (1 << 4) # define DCMP_CLOCK_GATE_DISABLE (1 << 3) # define MEC_CLOCK_GATE_DISABLE (1 << 2) # define MECO_CLOCK_GATE_DISABLE (1 << 1) -/** This bit must be set on 855,865. */ +/* This bit must be set on 855,865. */ # define SV_CLOCK_GATE_DISABLE (1 << 0) # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) @@ -1132,14 +1132,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) -/** This bit must always be set on 965G/965GM */ +/* This bit must always be set on 965G/965GM */ # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) -/** This bit must always be set on 965G */ +/* This bit must always be set on 965G */ # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) @@ -1178,7 +1178,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define BLC_PWM_CTL 0x61254 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) #define BACKLIGHT_MODULATION_FREQ_SHIFT2 (16) -/** +/* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * @@ -1188,7 +1188,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define BACKLIGHT_MODULATION_FREQ_MASK2 (0xffff << 16) #define BLM_LEGACY_MODE (1 << 16) -/** +/* * This is the number of cycles out of the backlight modulation cycle for which * the backlight is on. * @@ -1274,7 +1274,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) #define SDVO_INTERRUPT_ENABLE (1 << 26) -/** +/* * 915G/GM SDVO pixel multiplier. * * Programmed value is multiplier - 1, up to 5x. @@ -1289,15 +1289,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SDVOC_GANG_MODE (1 << 16) #define SDVO_ENCODING_SDVO (0x0 << 10) #define SDVO_ENCODING_HDMI (0x2 << 10) -/** Requird for HDMI operation */ +/* Requird for HDMI operation */ #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) #define SDVO_BORDER_ENABLE (1 << 7) #define SDVO_AUDIO_ENABLE (1 << 6) -/** New with 965, default is to be set */ +/* New with 965, default is to be set */ #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) -/** New with 965, default is to be set */ +/* New with 965, default is to be set */ #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) -/** 915/945 only, read-only bit */ +/* 915/945 only, read-only bit */ #define SDVOB_PCIE_CONCURRENCY (1 << 3) #define SDVO_DETECTED (1 << 2) /* Bits to be preserved when writing */ @@ -1398,22 +1398,22 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 #define DVO_SRCDIM_VERTICAL_SHIFT 0 -/** @defgroup LVDS +/* @defgroup LVDS * @{ */ -/** +/* * This register controls the LVDS output enable, pipe selection, and data * format selection. * * All of the clock/data pairs are force powered down by power sequencing. */ #define LVDS 0x61180 -/** +/* * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ # define LVDS_PORT_EN (1 << 31) -/** Selects pipe B for LVDS data. Must be set on pre-965. */ +/* Selects pipe B for LVDS data. Must be set on pre-965. */ # define LVDS_PIPEB_SELECT (1 << 30) /* on 965, dithering is enabled in this register, not PFIT_CONTROL */ @@ -1473,14 +1473,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ # define LVDS_POWER_DOWN_TRI_STATE (1 << 10) -/** +/* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) # define LVDS_A0A2_CLKA_POWER_UP (3 << 8) -/** +/* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. @@ -1488,7 +1488,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define LVDS_A3_POWER_MASK (3 << 6) # define LVDS_A3_POWER_DOWN (0 << 6) # define LVDS_A3_POWER_UP (3 << 6) -/** +/* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ @@ -1496,7 +1496,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define LVDS_CLKB_POWER_DOWN (0 << 4) # define LVDS_CLKB_POWER_UP (3 << 4) -/** +/* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. @@ -1505,7 +1505,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define LVDS_B0B3_POWER_DOWN (0 << 2) # define LVDS_B0B3_POWER_UP (3 << 2) -/** @} */ +/* @} */ #define DP_B 0x64100 #define DPB_AUX_CH_CTL 0x64110 @@ -1561,110 +1561,110 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* data lines active (both timing and colour) */ # define LVDS_B_POWER_UP (3 << 2) -/** @defgroup TV_CTL +/* @defgroup TV_CTL * @{ */ #define TV_CTL 0x68000 -/** Enables the TV encoder */ +/* Enables the TV encoder */ # define TV_ENC_ENABLE (1 << 31) -/** Sources the TV encoder input from pipe B instead of A. */ +/* Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) -/** Outputs composite video (DAC A only) */ +/* Outputs composite video (DAC A only) */ # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) -/** Outputs SVideo video (DAC B/C) */ +/* Outputs SVideo video (DAC B/C) */ # define TV_ENC_OUTPUT_SVIDEO (1 << 28) -/** Outputs Component video (DAC A/B/C) */ +/* Outputs Component video (DAC A/B/C) */ # define TV_ENC_OUTPUT_COMPONENT (2 << 28) -/** Outputs Composite and SVideo (DAC A/B/C) */ +/* Outputs Composite and SVideo (DAC A/B/C) */ # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) # define TV_TRILEVEL_SYNC (1 << 21) -/** Enables slow sync generation (945GM only) */ +/* Enables slow sync generation (945GM only) */ # define TV_SLOW_SYNC (1 << 20) -/** Selects 4x oversampling for 480i and 576p */ +/* Selects 4x oversampling for 480i and 576p */ # define TV_OVERSAMPLE_4X (0 << 18) -/** Selects 2x oversampling for 720p and 1080i */ +/* Selects 2x oversampling for 720p and 1080i */ # define TV_OVERSAMPLE_2X (1 << 18) -/** Selects no oversampling for 1080p */ +/* Selects no oversampling for 1080p */ # define TV_OVERSAMPLE_NONE (2 << 18) -/** Selects 8x oversampling */ +/* Selects 8x oversampling */ # define TV_OVERSAMPLE_8X (3 << 18) -/** Selects progressive mode rather than interlaced */ +/* Selects progressive mode rather than interlaced */ # define TV_PROGRESSIVE (1 << 17) -/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ +/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ # define TV_PAL_BURST (1 << 16) -/** Field for setting delay of Y compared to C */ +/* Field for setting delay of Y compared to C */ # define TV_YC_SKEW_MASK (7 << 12) -/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ +/* Enables a fix for 480p/576p standard definition modes on the 915GM only */ # define TV_ENC_SDP_FIX (1 << 11) -/** +/* * Enables a fix for the 915GM only. * * Not sure what it does. */ # define TV_ENC_C0_FIX (1 << 10) -/** Bits that must be preserved by software */ +/* Bits that must be preserved by software */ # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) # define TV_FUSE_STATE_MASK (3 << 4) -/** Read-only state that reports all features enabled */ +/* Read-only state that reports all features enabled */ # define TV_FUSE_STATE_ENABLED (0 << 4) -/** Read-only state that reports that Macrovision is disabled in hardware*/ +/* Read-only state that reports that Macrovision is disabled in hardware*/ # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) -/** Read-only state that reports that TV-out is disabled in hardware. */ +/* Read-only state that reports that TV-out is disabled in hardware. */ # define TV_FUSE_STATE_DISABLED (2 << 4) -/** Normal operation */ +/* Normal operation */ # define TV_TEST_MODE_NORMAL (0 << 0) -/** Encoder test pattern 1 - combo pattern */ +/* Encoder test pattern 1 - combo pattern */ # define TV_TEST_MODE_PATTERN_1 (1 << 0) -/** Encoder test pattern 2 - full screen vertical 75% color bars */ +/* Encoder test pattern 2 - full screen vertical 75% color bars */ # define TV_TEST_MODE_PATTERN_2 (2 << 0) -/** Encoder test pattern 3 - full screen horizontal 75% color bars */ +/* Encoder test pattern 3 - full screen horizontal 75% color bars */ # define TV_TEST_MODE_PATTERN_3 (3 << 0) -/** Encoder test pattern 4 - random noise */ +/* Encoder test pattern 4 - random noise */ # define TV_TEST_MODE_PATTERN_4 (4 << 0) -/** Encoder test pattern 5 - linear color ramps */ +/* Encoder test pattern 5 - linear color ramps */ # define TV_TEST_MODE_PATTERN_5 (5 << 0) -/** +/* * This test mode forces the DACs to 50% of full output. * * This is used for load detection in combination with TVDAC_SENSE_MASK */ # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) # define TV_TEST_MODE_MASK (7 << 0) -/** @} */ +/* @} */ -/** @defgroup TV_DAC +/* @defgroup TV_DAC * @{ */ #define TV_DAC 0x68004 -/** +/* * Reports that DAC state change logic has reported change (RO). * * This gets cleared when TV_DAC_STATE_EN is cleared */ # define TVDAC_STATE_CHG (1 << 31) # define TVDAC_SENSE_MASK (7 << 28) -/** Reports that DAC A voltage is above the detect threshold */ +/* Reports that DAC A voltage is above the detect threshold */ # define TVDAC_A_SENSE (1 << 30) -/** Reports that DAC B voltage is above the detect threshold */ +/* Reports that DAC B voltage is above the detect threshold */ # define TVDAC_B_SENSE (1 << 29) -/** Reports that DAC C voltage is above the detect threshold */ +/* Reports that DAC C voltage is above the detect threshold */ # define TVDAC_C_SENSE (1 << 28) -/** +/* * Enables DAC state detection logic, for load-based TV detection. * * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set * to off, for load detection to work. */ # define TVDAC_STATE_CHG_EN (1 << 27) -/** Sets the DAC A sense value to high */ +/* Sets the DAC A sense value to high */ # define TVDAC_A_SENSE_CTL (1 << 26) -/** Sets the DAC B sense value to high */ +/* Sets the DAC B sense value to high */ # define TVDAC_B_SENSE_CTL (1 << 25) -/** Sets the DAC C sense value to high */ +/* Sets the DAC C sense value to high */ # define TVDAC_C_SENSE_CTL (1 << 24) -/** Overrides the ENC_ENABLE and DAC voltage levels */ +/* Overrides the ENC_ENABLE and DAC voltage levels */ # define DAC_CTL_OVERRIDE (1 << 7) -/** Sets the slew rate. Must be preserved in software */ +/* Sets the slew rate. Must be preserved in software */ # define ENC_TVDAC_SLEW_FAST (1 << 6) # define DAC_A_1_3_V (0 << 4) # define DAC_A_1_1_V (1 << 4) @@ -1678,11 +1678,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define DAC_C_1_1_V (1 << 0) # define DAC_C_0_7_V (2 << 0) # define DAC_C_OFF (3 << 0) -/** @} */ +/* @} */ -/** +/* * CSC coefficients are stored in a floating point format with 9 bits of - * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, + * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2*-n, * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with * -1 (0x3) being the only legal negative value. */ @@ -1695,7 +1695,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TV_CSC_Y2 0x68014 # define TV_BY_MASK 0x07ff0000 # define TV_BY_SHIFT 16 -/** +/* * Y attenuation for component video. * * Stored in 1.9 fixed point. @@ -1712,7 +1712,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TV_CSC_U2 0x6801c # define TV_BU_MASK 0x07ff0000 # define TV_BU_SHIFT 16 -/** +/* * U attenuation for component video. * * Stored in 1.9 fixed point. @@ -1729,7 +1729,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TV_CSC_V2 0x68024 # define TV_BV_MASK 0x07ff0000 # define TV_BV_SHIFT 16 -/** +/* * V attenuation for component video. * * Stored in 1.9 fixed point. @@ -1737,307 +1737,307 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define TV_AV_MASK 0x000007ff # define TV_AV_SHIFT 0 -/** @defgroup TV_CSC_KNOBS +/* @defgroup TV_CSC_KNOBS * @{ */ #define TV_CLR_KNOBS 0x68028 -/** 2s-complement brightness adjustment */ +/* 2s-complement brightness adjustment */ # define TV_BRIGHTNESS_MASK 0xff000000 # define TV_BRIGHTNESS_SHIFT 24 -/** Contrast adjustment, as a 2.6 unsigned floating point number */ +/* Contrast adjustment, as a 2.6 unsigned floating point number */ # define TV_CONTRAST_MASK 0x00ff0000 # define TV_CONTRAST_SHIFT 16 -/** Saturation adjustment, as a 2.6 unsigned floating point number */ +/* Saturation adjustment, as a 2.6 unsigned floating point number */ # define TV_SATURATION_MASK 0x0000ff00 # define TV_SATURATION_SHIFT 8 -/** Hue adjustment, as an integer phase angle in degrees */ +/* Hue adjustment, as an integer phase angle in degrees */ # define TV_HUE_MASK 0x000000ff # define TV_HUE_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_CLR_LEVEL +/* @defgroup TV_CLR_LEVEL * @{ */ #define TV_CLR_LEVEL 0x6802c -/** Controls the DAC level for black */ +/* Controls the DAC level for black */ # define TV_BLACK_LEVEL_MASK 0x01ff0000 # define TV_BLACK_LEVEL_SHIFT 16 -/** Controls the DAC level for blanking */ +/* Controls the DAC level for blanking */ # define TV_BLANK_LEVEL_MASK 0x000001ff # define TV_BLANK_LEVEL_SHIFT 0 /* @} */ -/** @defgroup TV_H_CTL_1 +/* @defgroup TV_H_CTL_1 * @{ */ #define TV_H_CTL_1 0x68030 -/** Number of pixels in the hsync. */ +/* Number of pixels in the hsync. */ # define TV_HSYNC_END_MASK 0x1fff0000 # define TV_HSYNC_END_SHIFT 16 -/** Total number of pixels minus one in the line (display and blanking). */ +/* Total number of pixels minus one in the line (display and blanking). */ # define TV_HTOTAL_MASK 0x00001fff # define TV_HTOTAL_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_H_CTL_2 +/* @defgroup TV_H_CTL_2 * @{ */ #define TV_H_CTL_2 0x68034 -/** Enables the colorburst (needed for non-component color) */ +/* Enables the colorburst (needed for non-component color) */ # define TV_BURST_ENA (1 << 31) -/** Offset of the colorburst from the start of hsync, in pixels minus one. */ +/* Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 -/** Length of the colorburst */ +/* Length of the colorburst */ # define TV_HBURST_LEN_SHIFT 0 # define TV_HBURST_LEN_MASK 0x0001fff -/** @} */ +/* @} */ -/** @defgroup TV_H_CTL_3 +/* @defgroup TV_H_CTL_3 * @{ */ #define TV_H_CTL_3 0x68038 -/** End of hblank, measured in pixels minus one from start of hsync */ +/* End of hblank, measured in pixels minus one from start of hsync */ # define TV_HBLANK_END_SHIFT 16 # define TV_HBLANK_END_MASK 0x1fff0000 -/** Start of hblank, measured in pixels minus one from start of hsync */ +/* Start of hblank, measured in pixels minus one from start of hsync */ # define TV_HBLANK_START_SHIFT 0 # define TV_HBLANK_START_MASK 0x0001fff -/** @} */ +/* @} */ -/** @defgroup TV_V_CTL_1 +/* @defgroup TV_V_CTL_1 * @{ */ #define TV_V_CTL_1 0x6803c -/** XXX */ +/* XXX */ # define TV_NBR_END_SHIFT 16 # define TV_NBR_END_MASK 0x07ff0000 -/** XXX */ +/* XXX */ # define TV_VI_END_F1_SHIFT 8 # define TV_VI_END_F1_MASK 0x00003f00 -/** XXX */ +/* XXX */ # define TV_VI_END_F2_SHIFT 0 # define TV_VI_END_F2_MASK 0x0000003f -/** @} */ +/* @} */ -/** @defgroup TV_V_CTL_2 +/* @defgroup TV_V_CTL_2 * @{ */ #define TV_V_CTL_2 0x68040 -/** Length of vsync, in half lines */ +/* Length of vsync, in half lines */ # define TV_VSYNC_LEN_MASK 0x07ff0000 # define TV_VSYNC_LEN_SHIFT 16 -/** Offset of the start of vsync in field 1, measured in one less than the +/* Offset of the start of vsync in field 1, measured in one less than the * number of half lines. */ # define TV_VSYNC_START_F1_MASK 0x00007f00 # define TV_VSYNC_START_F1_SHIFT 8 -/** +/* * Offset of the start of vsync in field 2, measured in one less than the * number of half lines. */ # define TV_VSYNC_START_F2_MASK 0x0000007f # define TV_VSYNC_START_F2_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_V_CTL_3 +/* @defgroup TV_V_CTL_3 * @{ */ #define TV_V_CTL_3 0x68044 -/** Enables generation of the equalization signal */ +/* Enables generation of the equalization signal */ # define TV_EQUAL_ENA (1 << 31) -/** Length of vsync, in half lines */ +/* Length of vsync, in half lines */ # define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_SHIFT 16 -/** Offset of the start of equalization in field 1, measured in one less than +/* Offset of the start of equalization in field 1, measured in one less than * the number of half lines. */ # define TV_VEQ_START_F1_MASK 0x0007f00 # define TV_VEQ_START_F1_SHIFT 8 -/** +/* * Offset of the start of equalization in field 2, measured in one less than * the number of half lines. */ # define TV_VEQ_START_F2_MASK 0x000007f # define TV_VEQ_START_F2_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_V_CTL_4 +/* @defgroup TV_V_CTL_4 * @{ */ #define TV_V_CTL_4 0x68048 -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F1_MASK 0x003f0000 # define TV_VBURST_START_F1_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ # define TV_VBURST_END_F1_MASK 0x000000ff # define TV_VBURST_END_F1_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_V_CTL_5 +/* @defgroup TV_V_CTL_5 * @{ */ #define TV_V_CTL_5 0x6804c -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F2_MASK 0x003f0000 # define TV_VBURST_START_F2_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ # define TV_VBURST_END_F2_MASK 0x000000ff # define TV_VBURST_END_F2_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_V_CTL_6 +/* @defgroup TV_V_CTL_6 * @{ */ #define TV_V_CTL_6 0x68050 -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F3_MASK 0x003f0000 # define TV_VBURST_START_F3_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ # define TV_VBURST_END_F3_MASK 0x000000ff # define TV_VBURST_END_F3_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_V_CTL_7 +/* @defgroup TV_V_CTL_7 * @{ */ #define TV_V_CTL_7 0x68054 -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F4_MASK 0x003f0000 # define TV_VBURST_START_F4_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ # define TV_VBURST_END_F4_MASK 0x000000ff # define TV_VBURST_END_F4_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_SC_CTL_1 +/* @defgroup TV_SC_CTL_1 * @{ */ #define TV_SC_CTL_1 0x68060 -/** Turns on the first subcarrier phase generation DDA */ +/* Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA1_EN (1 << 31) -/** Turns on the first subcarrier phase generation DDA */ +/* Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA2_EN (1 << 30) -/** Turns on the first subcarrier phase generation DDA */ +/* Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA3_EN (1 << 29) -/** Sets the subcarrier DDA to reset frequency every other field */ +/* Sets the subcarrier DDA to reset frequency every other field */ # define TV_SC_RESET_EVERY_2 (0 << 24) -/** Sets the subcarrier DDA to reset frequency every fourth field */ +/* Sets the subcarrier DDA to reset frequency every fourth field */ # define TV_SC_RESET_EVERY_4 (1 << 24) -/** Sets the subcarrier DDA to reset frequency every eighth field */ +/* Sets the subcarrier DDA to reset frequency every eighth field */ # define TV_SC_RESET_EVERY_8 (2 << 24) -/** Sets the subcarrier DDA to never reset the frequency */ +/* Sets the subcarrier DDA to never reset the frequency */ # define TV_SC_RESET_NEVER (3 << 24) -/** Sets the peak amplitude of the colorburst.*/ +/* Sets the peak amplitude of the colorburst.*/ # define TV_BURST_LEVEL_MASK 0x00ff0000 # define TV_BURST_LEVEL_SHIFT 16 -/** Sets the increment of the first subcarrier phase generation DDA */ +/* Sets the increment of the first subcarrier phase generation DDA */ # define TV_SCDDA1_INC_MASK 0x00000fff # define TV_SCDDA1_INC_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_SC_CTL_2 +/* @defgroup TV_SC_CTL_2 * @{ */ #define TV_SC_CTL_2 0x68064 -/** Sets the rollover for the second subcarrier phase generation DDA */ +/* Sets the rollover for the second subcarrier phase generation DDA */ # define TV_SCDDA2_SIZE_MASK 0x7fff0000 # define TV_SCDDA2_SIZE_SHIFT 16 -/** Sets the increent of the second subcarrier phase generation DDA */ +/* Sets the increent of the second subcarrier phase generation DDA */ # define TV_SCDDA2_INC_MASK 0x00007fff # define TV_SCDDA2_INC_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_SC_CTL_3 +/* @defgroup TV_SC_CTL_3 * @{ */ #define TV_SC_CTL_3 0x68068 -/** Sets the rollover for the third subcarrier phase generation DDA */ +/* Sets the rollover for the third subcarrier phase generation DDA */ # define TV_SCDDA3_SIZE_MASK 0x7fff0000 # define TV_SCDDA3_SIZE_SHIFT 16 -/** Sets the increent of the third subcarrier phase generation DDA */ +/* Sets the increent of the third subcarrier phase generation DDA */ # define TV_SCDDA3_INC_MASK 0x00007fff # define TV_SCDDA3_INC_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_WIN_POS +/* @defgroup TV_WIN_POS * @{ */ #define TV_WIN_POS 0x68070 -/** X coordinate of the display from the start of horizontal active */ +/* X coordinate of the display from the start of horizontal active */ # define TV_XPOS_MASK 0x1fff0000 # define TV_XPOS_SHIFT 16 -/** Y coordinate of the display from the start of vertical active (NBR) */ +/* Y coordinate of the display from the start of vertical active (NBR) */ # define TV_YPOS_MASK 0x00000fff # define TV_YPOS_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_WIN_SIZE +/* @defgroup TV_WIN_SIZE * @{ */ #define TV_WIN_SIZE 0x68074 -/** Horizontal size of the display window, measured in pixels*/ +/* Horizontal size of the display window, measured in pixels*/ # define TV_XSIZE_MASK 0x1fff0000 # define TV_XSIZE_SHIFT 16 -/** +/* * Vertical size of the display window, measured in pixels. * * Must be even for interlaced modes. */ # define TV_YSIZE_MASK 0x00000fff # define TV_YSIZE_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_FILTER_CTL_1 +/* @defgroup TV_FILTER_CTL_1 * @{ */ #define TV_FILTER_CTL_1 0x68080 -/** +/* * Enables automatic scaling calculation. * * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. */ # define TV_AUTO_SCALE (1 << 31) -/** +/* * Disables the vertical filter. * * This is required on modes more than 1024 pixels wide */ # define TV_V_FILTER_BYPASS (1 << 29) -/** Enables adaptive vertical filtering */ +/* Enables adaptive vertical filtering */ # define TV_VADAPT (1 << 28) # define TV_VADAPT_MODE_MASK (3 << 26) -/** Selects the least adaptive vertical filtering mode */ +/* Selects the least adaptive vertical filtering mode */ # define TV_VADAPT_MODE_LEAST (0 << 26) -/** Selects the moderately adaptive vertical filtering mode */ +/* Selects the moderately adaptive vertical filtering mode */ # define TV_VADAPT_MODE_MODERATE (1 << 26) -/** Selects the most adaptive vertical filtering mode */ +/* Selects the most adaptive vertical filtering mode */ # define TV_VADAPT_MODE_MOST (3 << 26) -/** +/* * Sets the horizontal scaling factor. * * This should be the fractional part of the horizontal scaling factor divided @@ -2047,33 +2047,33 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ # define TV_HSCALE_FRAC_MASK 0x00003fff # define TV_HSCALE_FRAC_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_FILTER_CTL_2 +/* @defgroup TV_FILTER_CTL_2 * @{ */ #define TV_FILTER_CTL_2 0x68084 -/** +/* * Sets the integer part of the 3.15 fixed-point vertical scaling factor. * * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) */ # define TV_VSCALE_INT_MASK 0x00038000 # define TV_VSCALE_INT_SHIFT 15 -/** +/* * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. * * \sa TV_VSCALE_INT_MASK */ # define TV_VSCALE_FRAC_MASK 0x00007fff # define TV_VSCALE_FRAC_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_FILTER_CTL_3 +/* @defgroup TV_FILTER_CTL_3 * @{ */ #define TV_FILTER_CTL_3 0x68088 -/** +/* * Sets the integer part of the 3.15 fixed-point vertical scaling factor. * * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) @@ -2082,7 +2082,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ # define TV_VSCALE_IP_INT_MASK 0x00038000 # define TV_VSCALE_IP_INT_SHIFT 15 -/** +/* * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. * * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. @@ -2091,43 +2091,43 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ # define TV_VSCALE_IP_FRAC_MASK 0x00007fff # define TV_VSCALE_IP_FRAC_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_CC_CONTROL +/* @defgroup TV_CC_CONTROL * @{ */ #define TV_CC_CONTROL 0x68090 # define TV_CC_ENABLE (1 << 31) -/** +/* * Specifies which field to send the CC data in. * * CC data is usually sent in field 0. */ # define TV_CC_FID_MASK (1 << 27) # define TV_CC_FID_SHIFT 27 -/** Sets the horizontal position of the CC data. Usually 135. */ +/* Sets the horizontal position of the CC data. Usually 135. */ # define TV_CC_HOFF_MASK 0x03ff0000 # define TV_CC_HOFF_SHIFT 16 -/** Sets the vertical position of the CC data. Usually 21 */ +/* Sets the vertical position of the CC data. Usually 21 */ # define TV_CC_LINE_MASK 0x0000003f # define TV_CC_LINE_SHIFT 0 -/** @} */ +/* @} */ -/** @defgroup TV_CC_DATA +/* @defgroup TV_CC_DATA * @{ */ #define TV_CC_DATA 0x68094 # define TV_CC_RDY (1 << 31) -/** Second word of CC data to be transmitted. */ +/* Second word of CC data to be transmitted. */ # define TV_CC_DATA_2_MASK 0x007f0000 # define TV_CC_DATA_2_SHIFT 16 -/** First word of CC data to be transmitted. */ +/* First word of CC data to be transmitted. */ # define TV_CC_DATA_1_MASK 0x0000007f # define TV_CC_DATA_1_SHIFT 0 -/** @} +/* @} */ -/** @{ */ +/* @{ */ #define TV_H_LUMA_0 0x68100 #define TV_H_LUMA_59 0x681ec #define TV_H_CHROMA_0 0x68200 @@ -2136,7 +2136,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TV_V_LUMA_42 0x683a8 #define TV_V_CHROMA_0 0x68400 #define TV_V_CHROMA_42 0x684a8 -/** @} */ +/* @} */ #define PIPEA_DSL 0x70000 diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index e7567d2..a32871d 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -286,7 +286,7 @@ gen8_fill_ps(struct intel_batchbuffer *batch, return offset; } -/** +/* * gen7_fill_vertex_buffer_data populate vertex buffer with data. * * The vertex buffer consists of 3 vertices to construct a RECTLIST. The 4th @@ -327,7 +327,7 @@ gen7_fill_vertex_buffer_data(struct intel_batchbuffer *batch, return offset; } -/** +/* * gen6_emit_vertex_elements - The vertex elements describe the contents of the * vertex buffer. We pack the vertex buffer in a semi weird way, conforming to * what gen6_rendercopy did. The most straightforward would be to store @@ -384,7 +384,7 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) { GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); } -/** +/* * gen7_emit_vertex_buffer emit the vertex buffers command * * @batch