From patchwork Thu Jul 3 21:33:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 4477221 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D720B9F26C for ; Thu, 3 Jul 2014 21:33:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 07DA32038C for ; Thu, 3 Jul 2014 21:33:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 34B9820253 for ; Thu, 3 Jul 2014 21:33:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A63C26E782; Thu, 3 Jul 2014 14:33:27 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f177.google.com (mail-pd0-f177.google.com [209.85.192.177]) by gabe.freedesktop.org (Postfix) with ESMTP id D93C16E786 for ; Thu, 3 Jul 2014 14:33:26 -0700 (PDT) Received: by mail-pd0-f177.google.com with SMTP id y10so835492pdj.22 for ; Thu, 03 Jul 2014 14:33:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=t4OvjotthNZlqPG294kW0hzVzm+beN6ZNQQFs1BBSgE=; b=r2fcBwTjYiFWpoK2t6HcBJ8NePPDx/3uG8CazAWo2liQiek2QxcxOPzYpSRcPI1ncj KecWx5pbSsi2FPqo1/Pr0Y0xYl7MnG6+jJCwPRnPWxgRvqGDadN39lBnS5B0uTKFvkiy 1Ok7NFCMgddz40db96wfeMh3RlDAeQZI6ZMGFQTMCIzWt6oTVbjgdKdu3i2OX6SnZHbK Wey+JVc92A/Utn2YdXQsn2JLBsCEr0DyRvi7uMwWYyJfwAdiNORz+mCpHbBhW9ZEjAgP TnANEC7l1pnm9xvxuvPRAmY4Lj+Q1OkEesb4f7JSoKSzb6gZpDbiSfsOBvJ1Hup9awjP eDrw== X-Received: by 10.66.66.225 with SMTP id i1mr7204104pat.0.1404423206663; Thu, 03 Jul 2014 14:33:26 -0700 (PDT) Received: from rdvivi-bratislava.home (static-50-43-14-60.bvtn.or.frontiernet.net. [50.43.14.60]) by mx.google.com with ESMTPSA id js3sm42016885pbb.50.2014.07.03.14.33.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Jul 2014 14:33:25 -0700 (PDT) From: Rodrigo Vivi X-Google-Original-From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Jul 2014 17:33:03 -0400 Message-Id: <1404423186-2019-8-git-send-email-rodrigo.vivi@intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1404423186-2019-1-git-send-email-rodrigo.vivi@intel.com> References: <1404423186-2019-1-git-send-email-rodrigo.vivi@intel.com> MIME-Version: 1.0 Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH 07/10] drm/i915: HWS must be in the mappable region for g33 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson On g33, the documentation states "HWS_PGA: Format = Bits 28:12 of graphics memory address (bits 31:29 MBZ)." which translates to that the address of the HWS must be below 256MiB, which is conveniently the mappable aperture. This also appears to be true (but not documented as so) for gen4 and gen5. To generalise we force it into the low mappable region for all non-LLC platforms. If we locate the HWS at the top of the GTT the machine will hard hang during boot (fails on pnv, gm45, ilk and byt, but works on snb, ivb, hsw). v2: Add comments to explain why use PIN_MAPPABLE even though we have no intention of mapping the object. (Ville) Signed-off-by: Chris Wilson Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_ringbuffer.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2faef26..f49a3dd 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1331,6 +1331,7 @@ static int init_status_page(struct intel_engine_cs *ring) struct drm_i915_gem_object *obj; if ((obj = ring->status_page.obj) == NULL) { + unsigned flags; int ret; obj = i915_gem_alloc_object(ring->dev, 4096); @@ -1343,7 +1344,20 @@ static int init_status_page(struct intel_engine_cs *ring) if (ret) goto err_unref; - ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); + flags = 0; + if (!HAS_LLC(ring->dev)) + /* On g33, we cannot place HWS above 256MiB, so + * restrict its pinning to the low mappable arena. + * Though this restriction is not documented for + * gen4, gen5, or byt, they also behave similarly + * and hang if the HWS is placed at the top of the + * GTT. To generalise, it appears that all !llc + * platforms have issues with us placing the HWS + * above the mappable region (even though we never + * actualy map it). + */ + flags |= PIN_MAPPABLE; + ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); if (ret) { err_unref: drm_gem_object_unreference(&obj->base);