From patchwork Wed Jul 16 21:49:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Taylor, Clinton A" X-Patchwork-Id: 4571691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8E7BD9F37C for ; Wed, 16 Jul 2014 21:51:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E4329201EF for ; Wed, 16 Jul 2014 21:51:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 04CFF201E4 for ; Wed, 16 Jul 2014 21:51:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 791E989E5B; Wed, 16 Jul 2014 14:51:00 -0700 (PDT) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id D581889E43 for ; Wed, 16 Jul 2014 14:50:58 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 16 Jul 2014 14:50:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,673,1400050800"; d="scan'208";a="574315327" Received: from cataylo2-ubuntu64-12.jf.intel.com ([10.7.200.177]) by orsmga002.jf.intel.com with ESMTP; 16 Jul 2014 14:50:58 -0700 From: clinton.a.taylor@intel.com To: Intel-gfx@lists.freedesktop.org Date: Wed, 16 Jul 2014 14:49:40 -0700 Message-Id: <1405547387-14051-5-git-send-email-clinton.a.taylor@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405547387-14051-1-git-send-email-clinton.a.taylor@intel.com> References: <1405547387-14051-1-git-send-email-clinton.a.taylor@intel.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 04/11] CHROMIUM: drm/i915/vlv: Initialize pipe B backlight to A's value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky Not sure if this is needed or not. The code still falls back to a potentially bad value if PIPE_A was not set. Signed-off-by: Ben Widawsky Signed-off-by: Wayne Boyer Change-Id: I54eb5d4d9fd93e86878c9fa1daec19bdb6b3bd0b Reviewed-on: https://chromium-review.googlesource.com/196605 Reviewed-by: Aaron Durbin Tested-by: Wayne Boyer Commit-Queue: Wayne Boyer Conflicts: drivers/gpu/drm/i915/intel_panel.c --- drivers/gpu/drm/i915/intel_panel.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 40e0cb08..b3327d0 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -1080,15 +1080,24 @@ static int vlv_setup_backlight(struct intel_connector *connector) u32 ctl, ctl2, val; for_each_pipe(pipe) { - u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe)); + u32 duty = I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; + u32 freq = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; - /* Skip if the modulation freq is already set */ - if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK) + if (freq) { + /* Skip if the modulation freq is already set */ continue; + } + + if (WARN_ON(pipe == PIPE_A)) { + /* Assume BLC for pipe A is the default. Therefore, A + * must be non-zero. */ + freq = (VLV_DEFAULT_BACKLIGHT_MOD_FREQ << 16); + } else + freq = I915_READ(VLV_BLC_PWM_CTL(PIPE_A)) & ~BACKLIGHT_DUTY_CYCLE_MASK; - cur_val &= BACKLIGHT_DUTY_CYCLE_MASK; - I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) | - cur_val); + if (WARN_ON(freq == 0)) + freq = (VLV_DEFAULT_BACKLIGHT_MOD_FREQ << 16); + I915_WRITE(VLV_BLC_PWM_CTL(pipe), freq | duty); } ctl2 = I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));