From patchwork Thu Jul 24 23:18:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keith Packard X-Patchwork-Id: 4620431 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DA979C0514 for ; Thu, 24 Jul 2014 23:18:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AADBF201DD for ; Thu, 24 Jul 2014 23:18:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 78D7720170 for ; Thu, 24 Jul 2014 23:18:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6271B6E778; Thu, 24 Jul 2014 16:18:42 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id 968526E179; Thu, 24 Jul 2014 16:18:39 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by keithp.com (Postfix) with ESMTP id 58D4E760141; Thu, 24 Jul 2014 16:18:39 -0700 (PDT) X-Virus-Scanned: Debian amavisd-new at keithp.com Received: from keithp.com ([127.0.0.1]) by localhost (keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id ECR1mUas9JyH; Thu, 24 Jul 2014 16:18:33 -0700 (PDT) Received: by keithp.com (Postfix, from userid 1033) id 45FFE760131; Thu, 24 Jul 2014 16:18:33 -0700 (PDT) Received: from hiro.keithp.com (localhost [127.0.0.1]) by keithp.com (Postfix) with ESMTP id 271B1760109; Thu, 24 Jul 2014 16:18:33 -0700 (PDT) Received: by hiro.keithp.com (Postfix, from userid 1001) id 7AC2B74A584; Thu, 24 Jul 2014 16:18:32 -0700 (PDT) From: Keith Packard To: xorg-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Thu, 24 Jul 2014 16:18:20 -0700 Message-Id: <1406243908-1123-5-git-send-email-keithp@keithp.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1406243908-1123-1-git-send-email-keithp@keithp.com> References: <1406243908-1123-1-git-send-email-keithp@keithp.com> Subject: [Intel-gfx] [PATCH 04/12] Move intel_alloc_framebuffer to intel_memory.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP UXA and Glamor both share this function, so move it out of the UXA file. Signed-off-by: Keith Packard --- src/uxa/intel.h | 5 ++ src/uxa/intel_memory.c | 138 ++++++++++++++++++++++++++++++++++++++++++ src/uxa/intel_uxa.c | 158 ++++--------------------------------------------- 3 files changed, 154 insertions(+), 147 deletions(-) diff --git a/src/uxa/intel.h b/src/uxa/intel.h index 409635d..8110c2e 100644 --- a/src/uxa/intel.h +++ b/src/uxa/intel.h @@ -539,6 +539,11 @@ unsigned long intel_get_fence_pitch(intel_screen_private *intel, unsigned long p Bool intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling); void intel_set_gem_max_sizes(ScrnInfoPtr scrn); +unsigned int +intel_compute_size(struct intel_screen_private *intel, + int w, int h, int bpp, unsigned usage, + uint32_t *tiling, int *stride); + drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn, int width, int height, int cpp, int *out_stride, diff --git a/src/uxa/intel_memory.c b/src/uxa/intel_memory.c index 809b636..188a557 100644 --- a/src/uxa/intel_memory.c +++ b/src/uxa/intel_memory.c @@ -190,3 +190,141 @@ void intel_set_gem_max_sizes(ScrnInfoPtr scrn) */ intel->max_bo_size = intel->max_gtt_map_size; } + +unsigned int +intel_compute_size(struct intel_screen_private *intel, + int w, int h, int bpp, unsigned usage, + uint32_t *tiling, int *stride) +{ + int pitch, size; + + if (*tiling != I915_TILING_NONE) { + /* First check whether tiling is necessary. */ + pitch = (w * bpp + 7) / 8; + pitch = ALIGN(pitch, 64); + size = pitch * ALIGN (h, 2); + if (INTEL_INFO(intel)->gen < 040) { + /* Gen 2/3 has a maximum stride for tiling of + * 8192 bytes. + */ + if (pitch > KB(8)) + *tiling = I915_TILING_NONE; + + /* Narrower than half a tile? */ + if (pitch < 256) + *tiling = I915_TILING_NONE; + + /* Older hardware requires fences to be pot size + * aligned with a minimum of 1 MiB, so causes + * massive overallocation for small textures. + */ + if (size < 1024*1024/2 && !intel->has_relaxed_fencing) + *tiling = I915_TILING_NONE; + } else if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && size <= 4096) { + /* Disable tiling beneath a page size, we will not see + * any benefit from reducing TLB misses and instead + * just incur extra cost when we require a fence. + */ + *tiling = I915_TILING_NONE; + } + } + + pitch = (w * bpp + 7) / 8; + if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && pitch <= 256) + *tiling = I915_TILING_NONE; + + if (*tiling != I915_TILING_NONE) { + int aligned_h, tile_height; + + if (IS_GEN2(intel)) + tile_height = 16; + else if (*tiling == I915_TILING_X) + tile_height = 8; + else + tile_height = 32; + aligned_h = ALIGN(h, 2*tile_height); + + *stride = intel_get_fence_pitch(intel, + ALIGN(pitch, 512), + *tiling); + + /* Round the object up to the size of the fence it will live in + * if necessary. We could potentially make the kernel allocate + * a larger aperture space and just bind the subset of pages in, + * but this is easier and also keeps us out of trouble (as much) + * with drm_intel_bufmgr_check_aperture(). + */ + size = intel_get_fence_size(intel, *stride * aligned_h); + + if (size > intel->max_tiling_size) + *tiling = I915_TILING_NONE; + } + + if (*tiling == I915_TILING_NONE) { + /* We only require a 64 byte alignment for scanouts, but + * a 256 byte alignment for sharing with PRIME. + */ + *stride = ALIGN(pitch, 256); + /* Round the height up so that the GPU's access to a 2x2 aligned + * subspan doesn't address an invalid page offset beyond the + * end of the GTT. + */ + size = *stride * ALIGN(h, 2); + } + + return size; +} + +drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn, + int width, int height, int cpp, + int *out_stride, + uint32_t *out_tiling) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + uint32_t tiling; + int stride, size; + drm_intel_bo *bo; + + intel_set_gem_max_sizes(scrn); + + if (intel->tiling & INTEL_TILING_FB) + tiling = I915_TILING_X; + else + tiling = I915_TILING_NONE; + +retry: + size = intel_compute_size(intel, + width, height, + intel->cpp*8, 0, + &tiling, &stride); + if (!intel_check_display_stride(scrn, stride, tiling)) { + if (tiling != I915_TILING_NONE) { + tiling = I915_TILING_NONE; + goto retry; + } + + xf86DrvMsg(scrn->scrnIndex, X_ERROR, + "Front buffer stride %d kB " + "exceeds display limit\n", stride / 1024); + return NULL; + } + + bo = drm_intel_bo_alloc(intel->bufmgr, "front buffer", size, 0); + if (bo == NULL) + return FALSE; + + if (tiling != I915_TILING_NONE) + drm_intel_bo_set_tiling(bo, &tiling, stride); + + xf86DrvMsg(scrn->scrnIndex, X_INFO, + "Allocated new frame buffer %dx%d stride %d, %s\n", + width, height, stride, + tiling == I915_TILING_NONE ? "untiled" : "tiled"); + + drm_intel_bo_disable_reuse(bo); + + *out_stride = stride; + *out_tiling = tiling; + return bo; +} + diff --git a/src/uxa/intel_uxa.c b/src/uxa/intel_uxa.c index 717754f..5e1fbff 100644 --- a/src/uxa/intel_uxa.c +++ b/src/uxa/intel_uxa.c @@ -155,142 +155,6 @@ intel_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, return TRUE; } -static unsigned int -intel_uxa_compute_size(struct intel_screen_private *intel, - int w, int h, int bpp, unsigned usage, - uint32_t *tiling, int *stride) -{ - int pitch, size; - - if (*tiling != I915_TILING_NONE) { - /* First check whether tiling is necessary. */ - pitch = (w * bpp + 7) / 8; - pitch = ALIGN(pitch, 64); - size = pitch * ALIGN (h, 2); - if (INTEL_INFO(intel)->gen < 040) { - /* Gen 2/3 has a maximum stride for tiling of - * 8192 bytes. - */ - if (pitch > KB(8)) - *tiling = I915_TILING_NONE; - - /* Narrower than half a tile? */ - if (pitch < 256) - *tiling = I915_TILING_NONE; - - /* Older hardware requires fences to be pot size - * aligned with a minimum of 1 MiB, so causes - * massive overallocation for small textures. - */ - if (size < 1024*1024/2 && !intel->has_relaxed_fencing) - *tiling = I915_TILING_NONE; - } else if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && size <= 4096) { - /* Disable tiling beneath a page size, we will not see - * any benefit from reducing TLB misses and instead - * just incur extra cost when we require a fence. - */ - *tiling = I915_TILING_NONE; - } - } - - pitch = (w * bpp + 7) / 8; - if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && pitch <= 256) - *tiling = I915_TILING_NONE; - - if (*tiling != I915_TILING_NONE) { - int aligned_h, tile_height; - - if (IS_GEN2(intel)) - tile_height = 16; - else if (*tiling == I915_TILING_X) - tile_height = 8; - else - tile_height = 32; - aligned_h = ALIGN(h, 2*tile_height); - - *stride = intel_get_fence_pitch(intel, - ALIGN(pitch, 512), - *tiling); - - /* Round the object up to the size of the fence it will live in - * if necessary. We could potentially make the kernel allocate - * a larger aperture space and just bind the subset of pages in, - * but this is easier and also keeps us out of trouble (as much) - * with drm_intel_bufmgr_check_aperture(). - */ - size = intel_get_fence_size(intel, *stride * aligned_h); - - if (size > intel->max_tiling_size) - *tiling = I915_TILING_NONE; - } - - if (*tiling == I915_TILING_NONE) { - /* We only require a 64 byte alignment for scanouts, but - * a 256 byte alignment for sharing with PRIME. - */ - *stride = ALIGN(pitch, 256); - /* Round the height up so that the GPU's access to a 2x2 aligned - * subspan doesn't address an invalid page offset beyond the - * end of the GTT. - */ - size = *stride * ALIGN(h, 2); - } - - return size; -} - -drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn, - int width, int height, int cpp, - int *out_stride, - uint32_t *out_tiling) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - uint32_t tiling; - int stride, size; - drm_intel_bo *bo; - - if (intel->tiling & INTEL_TILING_FB) - tiling = I915_TILING_X; - else - tiling = I915_TILING_NONE; - -retry: - size = intel_uxa_compute_size(intel, - width, height, - intel->cpp*8, 0, - &tiling, &stride); - if (!intel_check_display_stride(scrn, stride, tiling)) { - if (tiling != I915_TILING_NONE) { - tiling = I915_TILING_NONE; - goto retry; - } - - xf86DrvMsg(scrn->scrnIndex, X_ERROR, - "Front buffer stride %d kB " - "exceeds display limit\n", stride / 1024); - return NULL; - } - - bo = drm_intel_bo_alloc(intel->bufmgr, "front buffer", size, 0); - if (bo == NULL) - return FALSE; - - if (tiling != I915_TILING_NONE) - drm_intel_bo_set_tiling(bo, &tiling, stride); - - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "Allocated new frame buffer %dx%d stride %d, %s\n", - width, height, stride, - tiling == I915_TILING_NONE ? "untiled" : "tiled"); - - drm_intel_bo_disable_reuse(bo); - - intel_set_gem_max_sizes(scrn); - *out_stride = stride; - *out_tiling = tiling; - return bo; -} - static Bool intel_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask) { @@ -906,10 +770,10 @@ static Bool intel_uxa_put_image(PixmapPtr pixmap, dri_bo *bo; /* Replace busy bo. */ - size = intel_uxa_compute_size(intel, - w, h, - pixmap->drawable.bitsPerPixel, pixmap->usage_hint, - &tiling, &stride); + size = intel_compute_size(intel, + w, h, + pixmap->drawable.bitsPerPixel, pixmap->usage_hint, + &tiling, &stride); if (size > intel->max_gtt_map_size) return FALSE; @@ -1169,9 +1033,9 @@ intel_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, if (h <= 16 && tiling == I915_TILING_Y) tiling = I915_TILING_X; } - size = intel_uxa_compute_size(intel, - w, h, pixmap->drawable.bitsPerPixel, usage, - &tiling, &stride); + size = intel_compute_size(intel, + w, h, pixmap->drawable.bitsPerPixel, usage, + &tiling, &stride); /* Fail very large allocations. Large BOs will tend to hit SW fallbacks * frequently, and also will tend to fail to successfully map when doing @@ -1324,10 +1188,10 @@ intel_uxa_share_pixmap_backing(PixmapPtr ppix, ScreenPtr slave, void **fd_handle tiling = I915_TILING_NONE; - size = intel_uxa_compute_size(intel, - ppix->drawable.width, ppix->drawable.height, - ppix->drawable.bitsPerPixel, INTEL_CREATE_PIXMAP_DRI2, - &tiling, &stride); + size = intel_compute_size(intel, + ppix->drawable.width, ppix->drawable.height, + ppix->drawable.bitsPerPixel, INTEL_CREATE_PIXMAP_DRI2, + &tiling, &stride); newbo = drm_intel_bo_alloc_for_render(intel->bufmgr, "pixmap",