| Message ID | 1406909608-13935-1-git-send-email-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2014-08-01 13:13 GMT-03:00 Rodrigo Vivi <rodrigo.vivi@intel.com>: > BDW has many other Display Engine interrupts and GT interrupts registers. > Collecting it properly on gpu_error_state. > > On debugfs all was properly listed already but besides we were also listing old > DEIER and GTIER that doesn't exist on BDW anymore. This was causing > unclaimed register messages: > > https://bugs.freedesktop.org/show_bug.cgi?id=81701 > > v2: Fix small issues of first version and don't read DEIER regs when pipe's > power well is disabled > v3: bikeshed accepted: use enum pipe pipe instead of int i for pipe interection Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++ > drivers/gpu/drm/i915/i915_drv.h | 4 +++- > drivers/gpu/drm/i915/i915_gpu_error.c | 32 ++++++++++++++++++++++++++++---- > 3 files changed, 35 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 9e737b7..b3493d3 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -703,6 +703,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > } > > for_each_pipe(pipe) { > + if (!intel_display_power_enabled(dev_priv, > + POWER_DOMAIN_PIPE(pipe))) > + continue; > + > seq_printf(m, "Pipe %c IMR:\t%08x\n", > pipe_name(pipe), > I915_READ(GEN8_DE_PIPE_IMR(pipe))); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 60227b2..d1ae952 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -317,7 +317,9 @@ struct drm_i915_error_state { > u32 eir; > u32 pgtbl_er; > u32 ier; > - u32 gtier; > + u32 gtier[4]; > + u32 deier[3]; > + u32 de_misc_ier; > u32 ccid; > u32 derrmr; > u32 forcewake; > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index c8f901f..402b621 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -328,6 +328,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > struct drm_i915_private *dev_priv = dev->dev_private; > struct drm_i915_error_state *error = error_priv->error; > struct drm_i915_error_object *obj; > + enum pipe pipe; > int i, j, offset, elt; > int max_hangcheck_score; > > @@ -359,8 +360,20 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); > err_printf(m, "EIR: 0x%08x\n", error->eir); > err_printf(m, "IER: 0x%08x\n", error->ier); > + if (IS_BROADWELL(dev)) { > + for_each_pipe(pipe) > + err_printf(m, "DEIER pipe %c: 0x%08x\n", > + pipe_name(pipe), > + error->deier[pipe]); > + for (i = 0; i < 4; i++) > + err_printf(m, "GTIER gt %d: 0x%08x\n", i, > + error->gtier[i]); > + err_printf(m, "DE_MISC_IER: 0x%08x\n", error->de_misc_ier); > + } else { > + err_printf(m, "IER: 0x%08x\n", error->ier); > + } > if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) > - err_printf(m, "GTIER: 0x%08x\n", error->gtier); > + err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); > err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); > err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); > err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); > @@ -1093,6 +1106,8 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > struct drm_i915_error_state *error) > { > struct drm_device *dev = dev_priv->dev; > + enum pipe pipe; > + int i; > > /* General organization > * 1. Registers specific to a single generation > @@ -1104,7 +1119,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > > /* 1: Registers specific to a single generation */ > if (IS_VALLEYVIEW(dev)) { > - error->gtier = I915_READ(GTIER); > + error->gtier[0] = I915_READ(GTIER); > error->ier = I915_READ(VLV_IER); > error->forcewake = I915_READ(FORCEWAKE_VLV); > } > @@ -1138,9 +1153,18 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > if (HAS_HW_CONTEXTS(dev)) > error->ccid = I915_READ(CCID); > > - if (HAS_PCH_SPLIT(dev)) { > + if (IS_BROADWELL(dev)) { > + for_each_pipe(pipe) > + if (intel_display_power_enabled(dev_priv, > + POWER_DOMAIN_PIPE(pipe))) > + error->deier[pipe] = > + I915_READ(GEN8_DE_PIPE_IER(pipe)); > + for (i = 0; i < 4; i++) > + error->gtier[i] = I915_READ(GEN8_GT_IER(i)); > + error->de_misc_ier = I915_READ(GEN8_DE_MISC_IER); > + } else if (HAS_PCH_SPLIT(dev)) { > error->ier = I915_READ(DEIER); > - error->gtier = I915_READ(GTIER); > + error->gtier[0] = I915_READ(GTIER); > } else if (IS_GEN2(dev)) { > error->ier = I915_READ16(IER); > } else if (!IS_VALLEYVIEW(dev)) { > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Aug 04, 2014 at 11:44:10AM -0300, Paulo Zanoni wrote: > 2014-08-01 13:13 GMT-03:00 Rodrigo Vivi <rodrigo.vivi@intel.com>: > > BDW has many other Display Engine interrupts and GT interrupts registers. > > Collecting it properly on gpu_error_state. > > > > On debugfs all was properly listed already but besides we were also listing old > > DEIER and GTIER that doesn't exist on BDW anymore. This was causing > > unclaimed register messages: > > > > https://bugs.freedesktop.org/show_bug.cgi?id=81701 > > > > v2: Fix small issues of first version and don't read DEIER regs when pipe's > > power well is disabled > > v3: bikeshed accepted: use enum pipe pipe instead of int i for pipe interection > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Both patches merged to dinq, thanks. -Daniel > > > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++ > > drivers/gpu/drm/i915/i915_drv.h | 4 +++- > > drivers/gpu/drm/i915/i915_gpu_error.c | 32 ++++++++++++++++++++++++++++---- > > 3 files changed, 35 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > index 9e737b7..b3493d3 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -703,6 +703,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > > } > > > > for_each_pipe(pipe) { > > + if (!intel_display_power_enabled(dev_priv, > > + POWER_DOMAIN_PIPE(pipe))) > > + continue; > > + > > seq_printf(m, "Pipe %c IMR:\t%08x\n", > > pipe_name(pipe), > > I915_READ(GEN8_DE_PIPE_IMR(pipe))); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 60227b2..d1ae952 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -317,7 +317,9 @@ struct drm_i915_error_state { > > u32 eir; > > u32 pgtbl_er; > > u32 ier; > > - u32 gtier; > > + u32 gtier[4]; > > + u32 deier[3]; > > + u32 de_misc_ier; > > u32 ccid; > > u32 derrmr; > > u32 forcewake; > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > > index c8f901f..402b621 100644 > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > > @@ -328,6 +328,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > > struct drm_i915_private *dev_priv = dev->dev_private; > > struct drm_i915_error_state *error = error_priv->error; > > struct drm_i915_error_object *obj; > > + enum pipe pipe; > > int i, j, offset, elt; > > int max_hangcheck_score; > > > > @@ -359,8 +360,20 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > > err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); > > err_printf(m, "EIR: 0x%08x\n", error->eir); > > err_printf(m, "IER: 0x%08x\n", error->ier); > > + if (IS_BROADWELL(dev)) { > > + for_each_pipe(pipe) > > + err_printf(m, "DEIER pipe %c: 0x%08x\n", > > + pipe_name(pipe), > > + error->deier[pipe]); > > + for (i = 0; i < 4; i++) > > + err_printf(m, "GTIER gt %d: 0x%08x\n", i, > > + error->gtier[i]); > > + err_printf(m, "DE_MISC_IER: 0x%08x\n", error->de_misc_ier); > > + } else { > > + err_printf(m, "IER: 0x%08x\n", error->ier); > > + } > > if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) > > - err_printf(m, "GTIER: 0x%08x\n", error->gtier); > > + err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); > > err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); > > err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); > > err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); > > @@ -1093,6 +1106,8 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > > struct drm_i915_error_state *error) > > { > > struct drm_device *dev = dev_priv->dev; > > + enum pipe pipe; > > + int i; > > > > /* General organization > > * 1. Registers specific to a single generation > > @@ -1104,7 +1119,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > > > > /* 1: Registers specific to a single generation */ > > if (IS_VALLEYVIEW(dev)) { > > - error->gtier = I915_READ(GTIER); > > + error->gtier[0] = I915_READ(GTIER); > > error->ier = I915_READ(VLV_IER); > > error->forcewake = I915_READ(FORCEWAKE_VLV); > > } > > @@ -1138,9 +1153,18 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > > if (HAS_HW_CONTEXTS(dev)) > > error->ccid = I915_READ(CCID); > > > > - if (HAS_PCH_SPLIT(dev)) { > > + if (IS_BROADWELL(dev)) { > > + for_each_pipe(pipe) > > + if (intel_display_power_enabled(dev_priv, > > + POWER_DOMAIN_PIPE(pipe))) > > + error->deier[pipe] = > > + I915_READ(GEN8_DE_PIPE_IER(pipe)); > > + for (i = 0; i < 4; i++) > > + error->gtier[i] = I915_READ(GEN8_GT_IER(i)); > > + error->de_misc_ier = I915_READ(GEN8_DE_MISC_IER); > > + } else if (HAS_PCH_SPLIT(dev)) { > > error->ier = I915_READ(DEIER); > > - error->gtier = I915_READ(GTIER); > > + error->gtier[0] = I915_READ(GTIER); > > } else if (IS_GEN2(dev)) { > > error->ier = I915_READ16(IER); > > } else if (!IS_VALLEYVIEW(dev)) { > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9e737b7..b3493d3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -703,6 +703,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data) } for_each_pipe(pipe) { + if (!intel_display_power_enabled(dev_priv, + POWER_DOMAIN_PIPE(pipe))) + continue; + seq_printf(m, "Pipe %c IMR:\t%08x\n", pipe_name(pipe), I915_READ(GEN8_DE_PIPE_IMR(pipe))); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 60227b2..d1ae952 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -317,7 +317,9 @@ struct drm_i915_error_state { u32 eir; u32 pgtbl_er; u32 ier; - u32 gtier; + u32 gtier[4]; + u32 deier[3]; + u32 de_misc_ier; u32 ccid; u32 derrmr; u32 forcewake; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index c8f901f..402b621 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -328,6 +328,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_error_state *error = error_priv->error; struct drm_i915_error_object *obj; + enum pipe pipe; int i, j, offset, elt; int max_hangcheck_score; @@ -359,8 +360,20 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); err_printf(m, "EIR: 0x%08x\n", error->eir); err_printf(m, "IER: 0x%08x\n", error->ier); + if (IS_BROADWELL(dev)) { + for_each_pipe(pipe) + err_printf(m, "DEIER pipe %c: 0x%08x\n", + pipe_name(pipe), + error->deier[pipe]); + for (i = 0; i < 4; i++) + err_printf(m, "GTIER gt %d: 0x%08x\n", i, + error->gtier[i]); + err_printf(m, "DE_MISC_IER: 0x%08x\n", error->de_misc_ier); + } else { + err_printf(m, "IER: 0x%08x\n", error->ier); + } if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) - err_printf(m, "GTIER: 0x%08x\n", error->gtier); + err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); @@ -1093,6 +1106,8 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, struct drm_i915_error_state *error) { struct drm_device *dev = dev_priv->dev; + enum pipe pipe; + int i; /* General organization * 1. Registers specific to a single generation @@ -1104,7 +1119,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, /* 1: Registers specific to a single generation */ if (IS_VALLEYVIEW(dev)) { - error->gtier = I915_READ(GTIER); + error->gtier[0] = I915_READ(GTIER); error->ier = I915_READ(VLV_IER); error->forcewake = I915_READ(FORCEWAKE_VLV); } @@ -1138,9 +1153,18 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, if (HAS_HW_CONTEXTS(dev)) error->ccid = I915_READ(CCID); - if (HAS_PCH_SPLIT(dev)) { + if (IS_BROADWELL(dev)) { + for_each_pipe(pipe) + if (intel_display_power_enabled(dev_priv, + POWER_DOMAIN_PIPE(pipe))) + error->deier[pipe] = + I915_READ(GEN8_DE_PIPE_IER(pipe)); + for (i = 0; i < 4; i++) + error->gtier[i] = I915_READ(GEN8_GT_IER(i)); + error->de_misc_ier = I915_READ(GEN8_DE_MISC_IER); + } else if (HAS_PCH_SPLIT(dev)) { error->ier = I915_READ(DEIER); - error->gtier = I915_READ(GTIER); + error->gtier[0] = I915_READ(GTIER); } else if (IS_GEN2(dev)) { error->ier = I915_READ16(IER); } else if (!IS_VALLEYVIEW(dev)) {
BDW has many other Display Engine interrupts and GT interrupts registers. Collecting it properly on gpu_error_state. On debugfs all was properly listed already but besides we were also listing old DEIER and GTIER that doesn't exist on BDW anymore. This was causing unclaimed register messages: https://bugs.freedesktop.org/show_bug.cgi?id=81701 v2: Fix small issues of first version and don't read DEIER regs when pipe's power well is disabled v3: bikeshed accepted: use enum pipe pipe instead of int i for pipe interection Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_gpu_error.c | 32 ++++++++++++++++++++++++++++---- 3 files changed, 35 insertions(+), 5 deletions(-)